Power amplifier arrangement

Details Power amplifier arrangement Power amplifier arrangement

2000-01-05

2001-04-10

Pascal, Robert (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including class d amplifier

C330S20700P, C330S273000

Reexamination Certificate

active

06215356

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to an amplifier arrangement.
Such an amplifier arrangement is already known in the art, e.g. from the U.S. Pat. No. 3,772,606 “Multi-level power amplifier”. Therein, amplifier arrangements consisting of a series connection of 4 transistors are shown. Indeed, in
FIGS. 2 and 3
of this prior art document, a first pair of transistors
39
and
40
, constituting a first emitter follower is coupled via a pair of diodes between a first pair of power supplies delivering a first pair of bias voltages. A second pair of power supplies, delivering to a second pair of power supply terminals a second pair of bias voltages of the same polarity and of larger amplitude than the first pair, is coupled between the outermost transistors
44
and
49
of
FIGS. 2 and 3
of this prior art document.
This configuration of
4
transistors in series, is generally known as the bipolar or push-pull variant of a class-G amplifier.
The four input terminals of this prior art class-G amplifier variant are coupled to the input signal source via bias means, the latter corresponding to the drive control circuit of claim
1
.
In
FIG. 2
of this prior art document, this bias means correspond to a pair of resistors, denoted
47
and
48
. In
FIG. 3
, the transistors are coupled in a different way to the input signal source, by means of a series connection of the resistors
60
,
56
,
58
and
62
, and the two diodes
64
and
66
. All these variants can however be considered as different embodiments of such a drive control circuit, which couples the input terminal of the arrangement to the different input terminals of the class-G power amplifier.
Such class-G power amplifiers have proven to be efficient from the point of view of power consumption. However, one major drawback is that they require a lot of silicon area if they have to be realized as an integrated circuit. Indeed, in for instance the bipolar or push-pull variant of the prior art embodiment, all four transistors have to be dimensioned such as to be able to deliver, resp. to sink, the largest possible power or current to, resp. from, the load. In applications such as audio amplifiers or Asymmetric Digital Subscriber Line amplifiers, this largest current is however only to be delivered in very exceptional circumstances. This is because the input signal has a high crest factor, meaning that in general, the input signal has a rather low average value, and that only in these very rarely occurring circumstances, the input signal peaks at this maximum level. Only in these circumstances this maximum current is to be delivered to the load. Nevertheless, since this high current is not only flowing through the transistors connected to the highest voltage power supplies, but also through the innermost transistors coupled to the lower voltage power supply, all four transistors are to be dimensioned to be able to carry these rarely occurring high currents.
SUMMARY OF THE INVENTION
An object of the present invention is thus to provide an amplifier arrangement of the above known type but requiring less chip area compared to the prior art class-G amplifier.
According to the invention, this object is achieved due to the fact that said amplifier arrangement further incorporates a second amplifier as is further described in the characteristic part of the claim
1
.
The addition of a second amplifier, biased by the second pair of bias voltages, and coupled in parallel with the class-G amplifier, will result in that the rarely occurring current peaks will now be distributed amongst the second amplifier and the class-G amplifier. The composing transistors can thereby be kept much smaller than the original class-G amplifier transistors. Since embodiments of such a second amplifier may only include two transistors, the total transistor area of the resulting arrangement will considerably be smaller than the original class-G arrangement. This will be explicitly shown in a further paragraph. The drive control circuit will thereby still guarantee the normal class-G operation, whereby from the inner class-G transition point, the second amplifier will also turn on. This inner class-G transition point in general is reached for input voltages equal to or exceeding to the voltage values of the first pair of bias voltages
Another characteristic feature of the present invention is that said second amplifier is a class-C amplifier.
In this way, also the power consumption of the total structure will still be comparable to that of the original class-G amplifier.
Yet a further characteristic feature of the present invention is mentioned in claim
3
.
In some embodiments of the amplifier arrangement, not only the drive control determines the onset of the second amplifier, but also the resistance in the class-G amplifier. This will be explained into more detail in the descriptive part of this document.
Still a further characteristic feature of the present invention is described in claim
4
.
This not only results in the reduction of the area of the complete arrangement, as compared to the prior art, but at the same time helps in realizing a difference in resistance in the current branches through both amplifiers. This difference thereby allows the current through the class-G amplifier to be rather limited. In addition, the output impedance of the complete amplifier arrangement can thereby also be tuned so as to obtain a smooth transition in operation from the class G to the class-G in parallel with the second amplifier.


REFERENCES:
patent: 3772606 (1973-11-01), Wachner
patent: 4160216 (1979-07-01), Thornton
patent: 4346349 (1982-08-01), Yokoyama
patent: 4688001 (1987-08-01), Dijkmans et al.
patent: 0 092 206 A2 (1983-10-01), None
patent: 55 165 006 (1980-12-01), None
Len Feldman, “Class G High Efficiency HI-FI Amplifier” Aug. 1976, pp. 47-49,87.
Raab, F., et al.: Average Efficiency of Class-G Power Amplifiers, IEEE 1986, p. 145.
Sampei, T., et al: “Highest Efficiency and Super Quality Audio Amplifier Using MOS Power FETS in Class G. Operation” IEEE 1978 pp. 300-307.

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