Amplifiers – With semiconductor amplifying device – Including plural stages cascaded
Reexamination Certificate
1999-04-30
2001-03-20
Pascal, Robert (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including plural stages cascaded
C330S12400D
Reexamination Certificate
active
06204731
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to power amplifiers, more particularly, but not exclusively, to power amplifiers used in portable telephones used in cellular telephone systems.
BACKGROUND OF THE INVENTION
Current digital mobile communications systems require RF power amplifiers in the handset transmitter to have high efficiency; linearity not only at high output levels but also at low output levels. These stringent requirements arise from the need of the cellular system and to further increase the system transmission data rates and to expand the capacity.
In a portable handset for use in such system, a two or three stage power amplifier is normally used to power the transmitter—which is essential to determine the talk time and the size of the handset. In order to ensure that the battery lasts as long as possible in such a handset it is important to ensure that power consumption is minimised.
It is known that in a portable handset the power supply in the transmitter consumes 70%-80% of the battery power. It is evident therefore that a high efficiency power amplifier is important if the power consumption of the handset is to be reduced.
Normally a high output power is required for the power amplifier in the handset if the handset is at a position remote from the base station. However, the handsets will be often sufficiently close to a base section to allow operation of the amplifier at a medium or low output power level.
It is also important to maintain as high as possible the power and efficiency (PAE) for the amplifier at low and medium output levels. Again the higher linearity is required of the amplifier to reduce adjacent channel power (ACP) leakage over the whole power range—especially at high power levels.
There are contradictions in the way one achieves linearity, power and efficiency in a power amplifier design. If high linearity is required for a power amplifier it is usual to bias the amplifier at a high quiescent current such as class A. The efficiency therefore becomes low compared with class B or class C amplifiers. However, if a power amplifier is biased at a low quiescent current high efficiency for the amplifier can be achieved but the linearity of the device falls. It is usual in power amplifier design to make a trade off between efficiency, linearity and output power in conjunction with the biasing point, matching circuits and the like.
Various suggestions have been made (see bibliography and end of description)
To increase the PAE at low and high output power levels some have proposed a scheme with switch circuits. In this scheme the switch circuit and one or more amplifier circuits are introduced to improve amplifier efficiency. The first amplifier circuit is designed to achieve a high PAE at high output power levels whilst the second amplifier is designed for high PAE at low output power levels. Thus at different power levels different power amplifiers are used to amplify the input signal. Therefore the amplifier can obtain high PAE at low output power levels but unfortunately it cannot improve the linearity of the power amplifier at high output power levels.
Another approach to increase the efficiency was suggested earlier (see Sato). In this scheme the gate voltage of the amplifier is varied according to the output power levels. At low output power levels, bias current for the power amplifier is named to low to achieve high efficiency. At high output power levels bias current for the power amplifier is adjusted high to achieve high linearity. Unfortunately the power sensor and bias control circuits are required to realise the bias control function which again increases complexity of the power amplifier.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a power amplifier which meets the above noted requirements whilst being significantly simpler than the proposals made so far.
In one aspect the invention provides a power amplifier having an input terminal for receiving a signal to be amplified and an output terminal to which the amplified signal is passed, the power amplifier comprising a plurality of cascaded amplifier stages one of which comprises a plurality of amplifiers connected in parallel with their input ports interconnected and their output ports interconnected.
Said one stage may be the last stage in said plurality of cascaded stages.
Said one stage may comprise two or more amplifiers at least one of which is biased at class AB and at least another of which is biased at class C.
In this arrangement when the power level of the input signal is low the class AB amplifier alone is operational and when the power level of the input signal becomes high both the class AB and class C amplifiers are operational.
Alternatively said one stage comprises two or more amplifiers at least one of which is biased at class AB and at least another of may be switchably biased at class AB or class C.
It is envisaged that the amplifier with switchable bias is biased at class C when the power level of the input signal is low and at class AB when the power level of the input signal is high.
Again, alternatively, the said one stage may comprise two or more amplifiers, each of which may be switchably biased at class AB or class C and the gates widths of which may be different.
In this arrangement one of the amplifiers comprising an FET with a smaller gate width may be biased at class AB whilst the others are biased at class C when the input power level is low and one of the amplifiers of larger gate width may be biased at class AB whilst the others are biased at class C when the input power level is medium, and all of the amplifiers biased at class AB when the input level is high.
The amplifier stages may comprise bipolar junction transistors or field effect transistors.
Means are preferably provided enabling the power to be divided to the input to each amplifier in said one stage and means enabling the outputs of each of said amplifiers to be combined.
There may be provided between the power dividing point to the input of each of said amplifiers a matching circuit enabling phase shifting to compensate for the amplitude and phase response of each of said amplifiers.
In said one stage there may be provided between the output ports of each of said amplifiers and the combining point a matching circuit enabling phase shifting to compensate for the amplitude and phase response of each of said amplifiers.
In another aspect the invention provides a power amplifier having an input terminal for receiving a signal to be amplified and an output terminal to which the amplified signal is passed, and which comprises a plurality of amplifiers connected in parallel with their input ports interconnected and their output ports interconnected.
There may be provided two or more amplifiers at least one of which is biased at class AB and at least another of which is biased at class C.
It may be arranged such that when the power level of the input signal is low the class AB amplifier alone is operational and when the power level of the input signal becomes high both the class AB and class C amplifiers are operational.
There may be provided two or more amplifiers at least one of which is biased at class AB and at least another of may be switchably biased at class AB or class C.
It may be arranged such that the amplifier with switchable bias is biased at class C when the power level of the input signal is low, and at class AB when the power level of the input signal is high.
There may be provided two or more amplifiers each of which may be switchably biased at class AB or class C and the gates widths of which are different.
It may be arranged such that the FET with a smaller gate width is biased at class AB and the other at class C when the input power is low, but the amplifier who's FET with a wider gate is biased at class AB and the other are biased at class C when the input power level is medium and in which all the amplifiers are biased to class AB when the input power level is HIGH
Preferably, the amplifiers comprise different threshold voltage fi
Jiang Cao
Nakamura Hiroshi
Xinwei Wang
Choe Henry
Oppenheimer Wolff & Donnelly LLP
Pascal Robert
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