Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With specified crystal plane or axis
Patent
1996-08-28
1998-01-13
Ngo, Ngan V.
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With specified crystal plane or axis
257272, 257280, H01L 2904, H01L 31036
Patent
active
057082928
ABSTRACT:
Variations in the waveform of high-frequency signals amplified by a field-effect transistor (FET) in a power amplification circuit due to changes in temperature are reduced. A FET having an n-type active layer, a source electrode, a drain electrode and a gate electrode is formed on a (1 0 0)-crystal plane of a semi-insulating GaAs substrate. The FET is protected by a passivation film. The angle .theta., formed between the longitudinal axial direction of the gate electrode and the <0 -1 -1>-direction, is set at an angle of from 0.degree. to 90.degree. corresponding to the impurity concentration of the n-type active layer, in order that the temperature coefficient of the FET threshold voltage becomes substantially equal to the temperature coefficient of the gate bias voltage applied from a power supply to the gate electrode. If the angle .theta. is set at 45.degree., then the temperature coefficient of the FET threshold voltage becomes zero.
REFERENCES:
patent: 5182233 (1993-01-01), Inoue
patent: 5442227 (1995-08-01), Fukaishi et al.
Furukawa Hidetoshi
Ueda Daisuke
Matsushita Electronics Corporation
Ngo Ngan V.
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