Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
1999-11-05
2001-06-19
Young, Brian (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S144000
Reexamination Certificate
active
06249239
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to potentiometric digital to analog converters (DAC's).
BACKGROUND OF THE INVENTION
DAC's are widely used in the electronic industry. By way of example, many application specific integrated circuits (ASIC's) employ one or more DAC's of the type shown in
FIG. 1
in which a string of serially connected resistors connected between two voltage supplies V
DD
and V
SS
has a tap provided at a selected point in the string, at R
DX
in the example, to provide a voltage of a certain fraction of the range between the two voltage supplies at V
OUT
. This simple arrangement has provided a relatively stable ratiometric output on the order of 1%. However, certain applications have tightened accuracy requirements and can no longer tolerate this level of DAC error. It has been estimated that the drift, thermal or temporal, of a 10 bit DAC can be 1-2 LSB (minimum step size) steps. The normalized magnitude, that is, the number of LSB steps, of this drift can be significantly larger for DAC's which span only a fraction of the supply range. Slight differences in impurity doping or in stress relief with change in temperature and over time can cause drift which will change the fractional output of a DAC.
SUMMARY OF THE INVENTION
An object of the invention is to provide a potentiometric DAC having improved output voltage stability. Another object is the provision of a potentiometric DAC which has a ratiometric output voltage having enhanced insensitivity to variability caused by manufacturing, both thermal and temporal, in individual resistor values. Yet another object of the invention is the provision of a potentiometric DAC free of the limitations of the prior art discussed above.
Briefly, in accordance with one embodiment of the invention, first and second single-pole-double-throw switches are connected to both end portions of a string of n serially connected resistors of like value between first and second voltage power supplies. First and second DAC tap positions are located at equal fractions of the difference between the supply voltages above and below the average value of the two voltage supplies. These two tap positions may or may not be symmetric about the DAC center position. The first tap position provides the desired output voltage for a first connectivity of the single-pole-double-throw switches. Likewise, the second tap position provides the desired output for the second connectivity arrangement of the single-pole-double-throw switches. The output voltage of the first tap position is connected to a first plate of a first capacitor by closing a switch during a portion of the first single-pole-double-throw switch connectivity. Similarly, the output voltage of the second tap position is connected to a first plate of a second capacitor by closing another switch during a portion of the second single-pole-double-throw switch connectivity. The first plates of the first and second capacitors are then connected together and to a first plate of a third capacitor by closing commonly activated switches for a brief period. The voltage present on the first plate of the third capacitor after opening the commonly actuated third and fourth switches represents the final DAC output voltage. The first plate of the third capacitor is also connected to the non-inverting input of an operational amplifier (or op-amp). The inverting input of the op-amp output; thereby buffering the DAC output voltage present at the non-inverting op-amp input. All capacitor second plates are connected to a fixed supply voltage. A clocking circuit is used to close switches at each end of the string of resistors to connect the first and second end portions of the string to the first and second voltage supplies, respectively, and to connect the first tap to the first capacitor to charge the capacitor and store the charge. Although an arrangement is described employing equal valued first and second capacitors and sampling tap voltages symmetric about the supply voltage average, equivalent arrangements appropriately varying the preceding quantities are also beneficial. The preferred embodiment employs a circuit with equivalently valued first and second capacitors and a third capacitor value significantly smaller than either the first or second capacitor to avoid voltage drop issues associated with charge redistribution. The clocking circuit then opens the first pole of the switches between the end portions and the voltage supplies and closes the second pole of the switch at each end of the string of resistors to reverse the connection of the voltage supplies to the string, that is, it closes switches to connect the second and first end portions of the string to the first and second voltage supplies, respectively, and connects the second tap to the second capacitor to charge the capacitor and store the charge. The switch between the second tap and the second capacitor is opened and the commonly operated switch is closed to average the charge of the two capacitors and to provide a voltage output of enhanced stability. Although the resistor string is shown and described as being made up of resistors of like value, resistor values of unlike value can be employed as long as the switching taps are symmetrical about the average voltage of the voltages at the supply connectivity switches. It is also to be noted that resistors may be placed between the connectivity switches and power supplies. This arrangement provides a stability benefit for the resistors between the two tap positions and the connectivity switches, and permits switching about the center of the DAC for DACs having equally valued resistors.
Additional objects and advantages of the invention will be set forth in part in the description which follows and in part will be obvious from the description. The objects and advantages of the invention may be realized and attained by means of the instrumentalities, combinations and methods particularly pointed out in the appended claims.
REFERENCES:
patent: 5617091 (1997-04-01), Uda
patent: 6163289 (2000-12-01), Ginetti
Baumann Russell E.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Young Brian
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