Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2002-02-25
2003-07-22
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S537000, C323S313000
Reexamination Certificate
active
06597236
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a reference potential generating circuit, a potential detecting circuit and a semiconductor integrated circuit device. More specifically, it relates to an intermediate potential generating circuit used in a semiconductor memory device, an internal potential detecting circuit for controlling an internal potential generating circuit used in a semiconductor memory device, and to a semiconductor integrated circuit device including the internal potential generating circuit.
2. Description of the Background Art
FIG. 81
is a schematic diagram showing a main structure of a dynamic random access memory (hereinafter referred to as a “DRAM”) which is one of semiconductor memory devices.
Referring to
FIG. 81
, the DRAM includes a bit line pair BL and /BL, word lines WL arranged in a direction orthogonal to the bit line pair BL and /BL, line BLI arranged orthogonal to the bit line pair BL and /BL for controlling connection/disconnection of a sense amplifier and an array side, memory cells arranged corresponding to crossings between bit line pair BL and /BL and word lines WL, sense amplifiers SAn and SAp amplifying the voltage generated between the bit line pair BL and /BL, and a precharge circuit PC for precharging the bit line pair BL and /BL to an intermediate potential (½) Vcc of the power supply potential Vcc.
The memory cell MC includes a transfer gate TG and a capacitor C, and it is adapted such that when the potential at word line WL rises, data generated on the bit line pair BL and /BL is written to the capacitor C, or the data stored in capacitor C is read to bit line pair BL and /BL.
Sense amplifiers SAn and SAp are formed by an N channel sense amplifier SAn and a P channel sense amplifier SAp. N channel sense amplifier SAn includes cross coupled two N channel MOS transistors. P channel sense amplifier SAp includes two cross coupled P channel MOS transistors.
Precharge circuit PC supplies the intermediate potential (½) Vcc from precharge line VBL to bit line pair BL and /BL, and equalizes both potentials of the bit line pair BL and /BL in response to a control signal from a equalizing line EQ.
Reading operation of the DRAM will be described with reference to a timing chart of FIG.
82
.
Before reading the data, bit line pair BL and /BL are precharged to the intermediate potential (½) Vcc. Then, when the potential of the word line WL increases to the boosted potential Vpp, the data in capacitor C is read to bit line BL through transfer gate TG, and therefore the potential of the bit line BL is shifted to the power supply potential Vcc or the ground potential Vss.
Then, when transfer gates S
0
and /S
0
(not shown) connected to sense amplifier driving lines SN and SP are rendered conductive, the potential of bit line BL attains to the ground potential Vss and the potential of bit line /BL attains to the power supply potential Vcc, for example.
As described above, in the DRAM, it is necessary to precharge the bit line pair BL and /BL to the intermediate potential (½) Vcc.
FIG. 83
is a schematic diagram showing the whole structure of a conventional intermediate potential generating circuit disclosed in U.S. Pat. No. 4,788,455.
Referring to
FIG. 83
, the intermediate potential generating circuit includes a reference potential generating stage
1
generating a reference potential V
ref
1
, a reference potential generating stage
2
generating a reference potential V
ref
2
, an output stage
3
responsive to these reference potential V
ref
1
and V
ref
2
for generating an intermediate potential (½) Vcc, and an output node
4
.
Reference potential generating stage
1
includes a resistance element
1
a,
an N channel MOS transistor
1
b,
an N channel MOS transistor
1
c
and a resistance element
1
d
connected in series between a power supply node
100
to which the power supply potential Vcc is applied and a ground node
200
to which the ground potential Vss is applied. Reference potential generating stage
2
includes a resistance element
2
a,
a P channel MOS transistor
2
b,
a P channel MOS transistor
2
c
and a resistance element
2
d
connected in series between power supply node
100
and ground node
200
. Output stage
3
includes an N channel MOS transistor
3
a
and a P channel MOS transistor
3
b
connected in series between power supply node
100
and ground node
200
.
The reference potential V
ref
1
generated at node N
1
is determined by a threshold voltage V
tn
of diode connected N channel MOS transistor
1
b.
The reference potential V
ref
2
generated at node N
2
is determined by the absolute value |V
tp
| of the threshold voltage of diode connected P channel MOS transistor
2
c.
Therefore, at the gate electrode of N channel MOS transistor
3
a
in output stage
3
, a voltage (½) Vcc+V
tn
higher than the intermediate potential by the threshold voltage is applied. To the gate electrode of P channel MOS transistor
3
b,
a potential (½) Vcc−|V
tp
| lower than the intermediate potential by the absolute value of the threshold voltage is applied. Therefore, an intermediate potential (½) Vcc is generated as the output potential V
out
at output node
4
.
FIG. 85
shows the whole structure of an intermediate potential generating circuit shown in
FIG. 4
of Japanese Patent Laying-Open No. 63-174115.
Referring to
FIG. 85
, the intermediate potential generating circuit includes reference potential generating stage
5
for generating two reference potentials, an output stage
3
and an output node
4
. The output stage
3
is the same as that shown in FIG.
83
.
The reference potential generating stage
5
of the intermediate potential generating circuit includes a P channel MOS transistor
5
a
having its gate elect-code connected to ground node
200
, a diode connected N channel MOS transistor
5
b,
a diode connected P channel MOS transistor
5
c,
and an N channel MOS transistor
5
d
having its gate connected to power supply node
100
.
Similar to the one described above, in this intermediate potential generating circuit, a potential higher than the intermediate potential by the threshold voltage is applied to the gate electrode of N channel MOS transistor
3
a
in output stage
3
, and a potential lower than the intermediate potential by the absolute value of the threshold voltage is applied to the gate electrode of P channel MOS transistor
3
b,
and hence the intermediate potential (½) Vcc is generated at the output node
4
.
FIG. 86
is a schematic diagram showing an example of a boosted potential detecting circuit used in a DRAM. The boosted potential Vpp is supplied as power supply to a word driver driving a word line, for example. Referring to
FIG. 86
, the boosted potential detecting circuit includes P channel MOS transistors
6
a
to
6
d
connected in series between a detecting node
804
and ground node
200
, and an inverter
7
. Transistors
6
a
to
6
d
are each diode connected. Inverter
7
consists of P channel MOS transistor
7
a
and an N channel MOS transistor
7
b.
In the boosted potential detecting circuit, when the potential at node NA is lower than the logical threshold value of inverter
7
, an enable signal GE at the H (logic high) level is generated at output node
801
. In response to the H level enable signal GE, the boosted potential generating circuit (not shown) is activated. Meanwhile, when the potential at node NA becomes higher than the logical threshold value of inverter
7
, an enable signal GE at the L (logic low) level is generated at output node
801
. In response to the L level enable signal GE, the boosted potential generating circuit is inactivated.
However, in the intermediate potential generating circuit shown in
FIG. 83
, in order to reduce through current flowing from power supply node
100
to ground node
200
in reference potential generating stage
1
, the values of resistance elements
1
a
and
1
d
must be set as
Komiya Yuichiro
Ooishi Tsukasa
Callahan Timothy P.
Englund Terry L.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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