Potential change suppressing circuit

Details Potential change suppressing circuit Potential change suppressing circuit

2000-11-30

2002-06-18

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With bootstrap circuit

C327S390000, C327S534000

Reexamination Certificate

active

06407628

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-342357, Dec. 1, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit provided with a circuit for limiting to a predetermined value or less a change in a potential which has been boosted from a power supply potential, and more particularly to a nonvolatile semiconductor memory integrated circuit or the like having a row decoder circuit for outputting the boosted potential to word lines.
In the nonvolatile semiconductor memory integrated circuit, it is necessary to apply the potential boosted to a level higher than the normal potential of the power supply at the time of writing or erasing data.
FIG. 5
is a circuit diagram showing an extracted part of a row decoder circuit and a prior art potential control circuit for outputting a potential boosted to a level higher than the normal power supply at the time of writing data in a conventional nonvolatile semiconductor memory integrated circuit.
In
FIG. 5
, a transistor
51
is provided at a final stage of the row decoder circuit, and the transistor
51
outputs the boosted potential to word line WL at the time of data writing. To node A to which one of the source or the drain of this transistor
51
is connected, a potential which is boosted at the time of driving the word line WL is supplied. A node B to which the other of the source and the drain of the transistor
51
is connected is connected to the corresponding word line WL. Furthermore, between a node C to which the boosted potential is supplied and a node D to which the gate of the transistor
51
is connected, the source-drain path of the transistor
52
is inserted. To a node E of the gate of the transistor
52
, a predetermined bias potential is supplied.
Furthermore, between the node D and a node F to which the boosted potential is supplied, a potential limiting circuit
53
for limiting the potential at the node D to less than the predetermined value is inserted. This potential limiting circuit
53
comprises two transistors
54
and
55
in which a gate is connected to respective source and the source-drain paths are connected in series. In this case, the transistors
54
and
55
are of N-channel enhancement type.
Next, an operation of the circuit of
FIG. 5
will be explained by referring to the timing chart of
FIGS. 6A through 6D
. Suppose that the boosted potential V
1
is supplied to the node E of the gate of the transistor
52
at the time of data writing.
In the beginning, a boosted potential V
1
is supplied to the node C at the time of data writing to the memory cell not shown connected to the word line WL. As shown in
FIG. 6A
, when the node C is set to the boosted potential V
1
, the transistor
52
is turned on. Then, as shown in
FIG. 6B
, the node D is charged to V
1
−Vt through this transistor
52
(where Vt denotes a threshold voltage of the transistor
52
), and the transistor
52
is cut off.
Next, as shown in
FIG. 6C
, the potential of the node A is changed from the ground potential to the boosted potential V
1
. Since the transistor
52
has been cut off and the node D is in the floating state, the rise in the channel potential of the transistor
51
causes the rise in the potential of the node D from V
1
−Vt to V
2
as shown in
FIG. 6
by means of the coupling of the channel region in the transistor
51
. When this potential V
2
is higher than the value (V
1
+Vt) obtained by adding the threshold voltage Vt of the transistor
51
to the potential V
1
of the node A, the transistor
51
is set to a sufficient ON state with the result that the boosted potential supplied to the node A is transmitted to the node B. As a result, as shown in
FIG. 6D
, the boosted potential V
1
is supplied to the word line WL.
In this manner, it is required to sufficiently increase the potential of the node D which is the gate node of the transistor
51
in order to transmit the potential V
1
which is boosted from the node A to the node B. However, when the potential of the node D becomes too high so that the potential of the node D exceeds a withstanding voltage of the transistor connected to this node D, for example, the transistor
52
, the transistor
52
will be broken.
The potential limiting circuit
53
is provided to restrict the potential of the node D so as to prevent the potential of the node D from exceeding the withstanding voltage of the transistor
52
. That is, when the potential of the node D becomes higher than the sum of the threshold voltages of the respective transistors
54
and
55
, namely 2 Vt higher than the potential of the node F, the node D is discharged to the node F via a series connection circuit of the transistors
54
and
55
with the result that the potential of the node D is restricted so that the potential does not become a certain potential or more. Here, for example, when the potential of the node F is set to be equal to the potential V
1
at the node A, the upper limit of the node D becomes V
1
+2 Vt.
By the way, in a circuit of
FIG. 5
, no problem arises when the potential V
1
supplied to the node F has a sufficient current supply capability as can be seen in the power supply given from the outside of the chip, and the level is maintained stably. However, in the case where the potential V
1
supplied to the node F is generated in the booster circuit or the like in the chip, the current supply capability is low. When the current is consumed with the operation of the other circuit, there is a possibility that the potential V
1
at the node F is lowered to a level less than the predetermined value. This leads to the restriction of the potential of the node D to a level less than needed with the result that the potential of the node D does not attain the target value, and a boosted potential having a sufficient value can not be supplied to the word line WL.
In such a situation, conventionally, a circuit shown in
FIG. 7
is provided. This circuit is constituted in such a manner that the potential generated in the booster circuit
76
in the chip is supplied to the node F of the potential limiting circuit
53
via a transistor
77
which is diode-connected. Incidentally, the potential generated in the booster circuit
76
is also supplied to the other circuit
78
in the same chip.
In this circuit arrangement, the current is consumed in another circuit
78
. Since a gate of the transistor
77
is connected either to the source and the drain to form a diode-connection and the transistor
77
having a rectifying characteristic is connected between the booster circuit
76
and the node F, even when an output potential from the booster circuit
76
is lowered, the potential of the node F is not lowered.
By the way, as shown in
FIG. 7
, the capacity
71
is connected between the node F and the ground potential. This capacity
71
is provided for stabilizing the potential of the node F. When the potential limiting circuit
53
is operated, an excess charge at the node D is discharged toward the node F. No problem arises when the discharged charge is small as compared with the value of the capacity
71
. Otherwise, since the node F is in the floating state, the node F rises to a level higher than the potential set with the output of the booster circuit
76
. In this case, the charge of the node D is not discharged, and the intended effect of the potential limiting circuit
53
is lost.
Under these circumstances, it is considered that the value of the capacity
71
is enlarged. However, in the case where a plurality of potential limiting circuits
53
are connected to the node F, and these plurality of potential limiting circuits
53
are operated at the same time, the discharged charge quantity to the node F will become very large. Since it is necessary to make an attempt of increasing the capacity
71
along with the enlargement of the disc

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