Post-write address word correction in cache memory system

Details Post-write address word correction in cache memory system Post-write address word correction in cache memory system

1977-06-13

1978-05-30

Springborn, Harvey E.

Boots, shoes, and leggings

G06F 1108

Patent

active

040927130

ABSTRACT:
An apparatus for and a method of providing error correction of the address word of a cache memory system (CMS) utilizing post-write storage of the least recently used (LRU) block of data words. Error correction circuitry (ECC) is provided at the output of the address buffer (CAB) portion of the cache memory system so that the address word that specifies the addressable location in the main storage unit (MSU) into which the block of data words, which block of data words is stored in the data buffer (CDB) portion of the cache memory, is to be stored or written-back is error corrected upon readout. This error correction of the address word ensures that correctable errors in the address buffer provided address words do not generate a Miss signal by the storage interface unit (SIU) which, in turn, requires a MSU reference even though the desired address word and the associated data word are available in the cache memory system.

REFERENCES:
patent: 3588829 (1971-06-01), Boland et al.
patent: 3786427 (1974-01-01), Schmidt et al.
patent: 3840862 (1974-10-01), Ready
patent: 3896419 (1975-07-01), Lange et al.
patent: 3967247 (1976-06-01), Anderson et al.

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