Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2003-01-14
2004-01-06
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S424000, C438S425000, C438S757000, C438S763000
Reexamination Certificate
active
06673696
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related to integrated circuit (IC) devices and to processes of making IC devices. More particularly, the present invention relates to a method of forming trench isolation structures on substrates or layers including germanium.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs) include a multitude of transistors formed on a semiconductor substrate. Various methods of forming transistors on a semiconductor substrate are known in the art. Generally, transistors are isolated from each other by insulating or isolation structures.
One method of forming transistors on a silicon substrate involves the well-known Local Oxidation of Silicon (LOCOS) process. A conventional LOCOS process typically includes the following simplified steps. First, a silicon nitride layer is thermally grown on the silicon substrate. Generally, conventional LOCOS processes require a high quality, thermally grown silicon nitride layer to avoid delamination and other processing problems. Next, using a lithography and etch process, the nitride layer is selectively removed to produce a pattern where transistor source/drain areas are to be located. After patterning the source/drain areas, a field oxide is grown. As oxide growth is inhibited where the nitride layer still remains, the oxide only grows on the silicon substrate exposed during the source/drain patterning step. Finally, after oxide growth is complete, the remaining portions of the nitride layer are removed, leaving only the oxidized source/drain areas on the exposed silicon substrate.
Another process for forming insulating structures and defining source and drain regions is a shallow trench isolation (STI) process. A conventional STI process typically includes the following simplified steps. First, a silicon nitride layer is thermally grown or deposited onto the silicon substrate. Next, using a lithography and etch process, the silicon nitride layer is selectively removed to produce a pattern where transistor source/drain areas are to be located. After patterning the source/drain areas, the substrate is etched to form trenches. After the trenches are formed, a liner is thermally grown on the exposed surfaces of the trench. The liner oxide is typically formed at a very high temperature in a hydrochloric (HCI) acid ambient. An insulative material, such as, silicon dioxide (SiO
2
), is blanket deposited over the nitride layer and the liner oxide within the trench. The insulative material is polished to create a planar surface. The nitride layer is subsequently removed to leave the oxide structures within the trenches.
Shallow trench isolation (STI) structures are utilized in strained silicon (SMOS) processes. SMOS processes are utilized to increase transistor (MOSFET) performance by increasing the carrier mobility of silicon, thereby reducing resistance and power consumption and increasing drive current, frequency response and operating speed. Strained silicon is typically formed by growing a layer of silicon on a silicon germanium substrate or layer.
The silicon germanium lattice associated with the silicon germanium substrate is generally more widely spaced than a pure silicon lattice, with spacing becoming wider with a higher percentage of germanium. Because the silicon lattice aligns with the larger silicon germanium lattice, a tensile strain is created in the silicon layer. The silicon atoms are essentially pulled apart from one another.
Relaxed silicon has a conductive band that contains six equal valence bands. The application of tensile strain to the silicon causes four of the valence bands to increase in energy and two of the valence bands to decrease in energy. As a result of quantum effects, electrons effectively weigh 30 percent less when passing through the lower energy bands. Thus, the lower energy bands offer less resistance to electron flow. In addition, electrons meet with less vibrational energy from the nucleus of the silicon atom, which causes them to scatter at a rate of 500 to 1000 times less than in relaxed silicon. As a result, carrier mobility is dramatically increased in strained silicon compared to relaxed silicon, providing an increase in mobility of 80% or more for electrons and 20% or more for holes. The increase in mobility has been found to persist for current fields up to 1.5 megavolts/centimeter. These factors are believed to enable a device speed increase of 35% without further reduction of device size, or a 25% reduction in power consumption without a reduction in performance.
The use of germanium in SMOS processes can cause germanium contamination problems for IC structures, layers, and equipment. In particular, germanium outgassing or outdiffusion can contaminate various components associated with the fabrication equipment and integrated circuit structures associated with the processed wafer. Further, germanium outgassing can negatively impact the formation of thin films. In addition, germanium outdiffusion can cause germanium accumulation or “pile-up” at the interface of the liner, thereby causing reliability issues for the STI structure.
Germanium outgassing can be particularly problematic at the very high temperatures and HCI ambient environments associated with the liner of a shallow trench isolation (STI) structure. For example, conventional STI liner oxide processes can utilize temperatures of approximately 1000° C., which enhance germanium outgassing.
Thus, there is a need for an STI liner which can be formed without causing significant germanium outdiffusion. Further still, there is a need for a process of forming high quality oxides with good compatibility and yet are not susceptible to germanium outgassing. Further still, there is a need for an SMOS trench liner formation process. Yet further, there is a need for a liner formation process that is not as susceptible to germanium outgassing. Further still, there is a need for an STI process that does not utilize high temperature to thermally grow liners when germanium trenches are exposed.
SUMMARY OF THE INVENTION
An exemplary embodiment relates to a method of manufacturing an integrated circuit. The integrated circuit includes trench isolation regions in a substrate including germanium. The method includes forming a silicon nitride layer above the substrate, and selectively etching the silicon nitride layer to form apertures associated with locations of the trench isolation (STI) regions. The method also includes forming trenches in the substrate at the locations, forming trench fill material in the trenches at a low temperature, and forming oxide liners in the trenches of the substrate in a high temperature process.
Yet another exemplary embodiment relates to a method of forming shallow trench isolation regions in a semiconductor layer. The method includes providing a hard mask layer above the semiconductor layer, providing a photoresist layer above the hard mask layer, and selectively removing portions of the photoresist layer in a photolithographic process. The method further includes removing the hard mask layer at locations, forming trenches in the hard mask layer under the locations, filling the trench with an insulative material in a low temperature process, and forming a liner in the trenches in a high temperature process.
Yet another exemplary embodiment relates to a method of forming a liner in a trench in a germanium containing layer. The method includes selectively etching the germanium containing layer to form the trench, filling the trench with an insulative material in a low temperature process and performing high temperature oxidation to form the liner in the trench.
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Arasnia Farzad
Ngo Minh-Van
Ziang Qi
Advanced Micro Devices , Inc.
Foley & Lardner
Lebentritt Michael S.
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