Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Packaging or treatment of packaged semiconductor
Reexamination Certificate
1998-10-09
2001-04-17
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making device or circuit emissive of nonelectrical signal
Packaging or treatment of packaged semiconductor
C438S026000, C438S034000, C257S659000
Reexamination Certificate
active
06218205
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The field of Microelectromechanical Systems (MEMS) uses a variety of fabrication technologies, such as surface micromachining developed for the integrated circuit industry, to create highly miniaturized mechanical devices (usually 1 &mgr;m to 1 mm in size) on a microelectronic chip. This invention is in the field of microelectromechanical systems (MEMS and in particular relates to the post-process deposition of some material onto MEMS devices.
2. Description of the Prior Art
The majority of microelectromechanical systems (MEMS) in use today are fabricated in a variety of surface micromachining processes. Surface micromachined devices are formed by the alternate deposition of structural layers to form the device and sacrificial spacer layers to provide mechanical and electrical isolation. Polycrystalline silicon (polysilicon) is the most commonly used structural material and silicon dioxide (oxide) glass is the most commonly used sacrificial material. These layers, formed above a silicon substrate isolated with a layer of silicon nitride, are patterned (using the same advanced photolithography technology employed by the microelectronics industry) to form intricate structures such as motors, gears, mirrors, and various sensors. Cuts made through the oxide layers are used to anchor the upper structural levels to the substrate or to the underlying mechanical structures. At the end of the process, the sacrificial layers are removed using various techniques, such as a hydrofluoric acid release etch, which frees the device to move relative to the substrate. (M. A. Michalicek, J. H. Comtois, and H. K. Schriner, “Design and fabrication of optical MEMS using a four-level, planarized, surface-micromachined polysilicon5 process,”
Proc. SPIE,
Vol. 3276, pp. 48-55, 1998.)
The complexity of the micromachines that can be manufactured in a given process is a function of the number of independent layers of structural material the technology provides. A single independent level of structural material limits designers to simple sensors. Geared mechanisms require two releasable structural layers, a Poly-1 layer to form the gears and a Poly-2 layer to form the locking hub above the ground layer (Poly-0). Motorized geared mechanisms require a minimum of three independent levels. Far more complex mechanisms and systems require even more structural layers.
Surface micromachining fabrication of electronics and MEMS is well developed and widely used both privately and commercially. Countless companies, universities, and government agencies have fabricated micromechanical devices for the last 10 years or more. However, designers are limited to the layers that are offered by the foundry. For instance, the Multi-User MEMS Process (MUMPs) offered commercially by the Microelectronics Center of North Carolina (MCNC) has three layers of polysilicon and one layer of gold that the engineer can use to build his or her devices.
Deposition of materials onto parts of these micromechanical devices is frequently required. Currently, a designer is limited to the layer provided by the foundry or must spent considerable time and money duplicating the foundry process just to add another layer after the chip was fabricated. This process requires numerous photolithographic steps to accomplish the deposition of material in only the locations on the chip that the designer wished. The present invention simplifies this post-process deposition of materials onto MEMS devices.
Using the present invention, this can be done using a common sputtering or evaporating machine once the bond pads, wiring and other sensitive structures have been shielded by a masking surface that is built into the design and fabricated along with the devices on the chip. The shield is used to catch the excess material that would normally be deposited onto wiring or other features that the designer did not wish covered. The material is simply deposited onto the entire surface of the chip that has been designed with a deposition shield. All exposed surfaces, such as the shield and the structures requiring the deposition, are coated whereas all other structures beneath the shield, such as wiring and mechanical support assemblies, are not coated. Therefore, the designer no longer has to rely on the expensive and time-consuming approach of using standard lithography to deposit materials onto certain, but not all, features on the chip. The designer can now determine the devices he or she wants coated before the chip is fabricated and simply build the shield around those devices out of the same layers of material provided by the foundry.
SUMMARY OF THE INVENTION
Post-process deposition shields are built into the design layout of MEMS devices in the present invention. These shields isolate each bond pad and allow no address wiring or sensitive structures to be exposed anywhere on the chip. The support posts of these shields are recessed a certain distance to ensure that even a worst-case deposition of a conductive material will not short the bond pads or wiring to the shields. Additionally, since the material is deposited by simple sputtering or evaporating deposition machines, the designer can now choose any material to be deposited and not be limited by what the foundry has to offer. The designer can choose a material based on optimized material properties, thereby making it easier and more effective to fabricate any given device that requires a material coating.
REFERENCES:
patent: 5216490 (1993-06-01), Greiff
“Development of advanced second-generation micromirror devices fabricated in a four-level, planarized surface-micromachined polycrystalline silicon process,” Michalicke et al., SPIE vol.3292 Jan. 28, 1998.*
“Design and characterization of next-generation micromirrors fabricated in a four-level, planarized surface-micromachined polycrystalline silicon process,” Michalicek et al. IEEE Oct. 10, 1997.*
“Design and fabrication of optical MEMS using a four-level, planarized, surface-micromachined polycrystalline silicon process,” SPIE Jan. 26, 1998.*
M. A. Michalicek, J. H. Comtois, and H. K. Schriner, “Design and fabrication of optical MEMS using a four-level, planarized, surface-micromachined polysilicon5 process,”Proc. SPIE, vol. 3276, pp. 48-55, 1998.
M. A. Michalicek, J. H. Comtois, and H. K. Schriner, “Development of advanced second-generation micromirror devices fabricated in a four-level, planarized, surface-micromachined polysilicon process,”Proc. SPIE, vol. 3292, pp. 71-80, 1998.
M. A. Michalicek, J. H. Comtois, and C. C. Barron, “Design and characterization of next-generation micromirrors fabricated in a four-level, planarized, surface-micromachined polysilicon process,”Proc. Innovative Systems In Silicon, 2nd Ed., IEEE Press, pp. 144-154, 1997.
Berezny Nema
Bowers Charles
Callahan Kenneth E.
The United States of America as represented by the Secretary of
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