Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2000-08-07
2003-10-14
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S745000, C438S753000, C438S754000
Reexamination Certificate
active
06632743
ABSTRACT:
TECHNICAL FIELD
This invention relates to microelectronic device fabrication, and more particularly to processes and compositions for cleaning microelectronic substrates or wafers.
BACKGROUND OF THE INVENTION
Microelectronic device fabrication typically requires numerous steps from the manufacturing of microelectronic substrates, such as silicon wafers, to the formation of discrete components on the microelectronic substrate. The steps often include planarization, depositioning, and etching.
Planarization may be accomplished through either mechanical planarization or chemical-mechanical planarization techniques. Mechanical planarization involves the removal of a surface layer of material from a substrate by a coarse pad. Chemical-mechanical planarization (CMP) involves the application of a specially formulated slurry to a surface of a substrate and the agitation of the slurry by a scrubbing pad to achieve a highly planarized surface. Planarization is an important step in preparing the substrate for the depositioning and etching steps which form the microelectronic components on the substrate's surface. The depositioning steps employ various processes to form layers on the surface of the substrate from a variety materials, such as oxides and polysilicon. The etching steps employ various processes to remove material from the layers formed on the substrate surface. Etching may involve the complete removal of a layer, such as the complete removal of a native oxide layer from a polysilicon layer. Etching may also involve the removal of a portion of a layer to define specific geometries in the layer, such as the etching of a polysilicon layer. The formation of the microelectronic devices will often employ numerous successive depositioning and etching steps.
Clean substrates are critical to obtaining high yields in microelectronic device fabrication. Numerous contaminants can interfere with fabrication and are generally classified as being either particulates or films. These contaminants can occur from a variety of sources and may include contaminants such as: silicon dust, quartz dust, atmospheric dust, and particles from the clean room personnel and particles from the processing equipment. Often, the source of the contamination will be one of the processing steps. While the fabrication process is generally designed to eliminate as many sources of contamination as possible, numerous extra processing steps must be performed to remove contaminants to prevent interference by the contaminants with successive processing steps. These cleaning steps may include steps for removing soluble contaminates from the substrate, such as washing the substrate by: immersion in a bath, immersion in a dump rinser, use of centrifugal spray cleaners, and use of rinser dryers. These steps usually employ deionized (DI) water as the principal solvent. Removal of insoluble particulate contamination may be performed through other or additional steps, such as: ultrasonic scrubbing, high-pressure spraying and, or, mechanical scrubbing.
The planarization process is a significant source of particulate contaminants. In particular, the planarization, particularly the CMP process leaves carbon on the substrate surface. This byproduct of the planarization process interferes with an acid etching step that removes a native oxide layer that typically builds up on the substrate surface. The incomplete removal of the native oxide layer interferes with the subsequent removal of polysilicon from the backside of the substrate through a polysilicon etching step.
SUMMARY OF THE INVENTION
The present invention overcomes the limitations of the prior art by washing a microelectronic substrate with an ozonated solution after planarization and, or, before acid etching of an oxide layer formed on the substrate. The ozonated solution preferably comprises DI water into which ozone has been dispersed.
In one exemplary embodiment, ozone is introduced into a tank of DI water and allowed to saturate the DI water for approximately one minute. The microelectronic substrates are dipped into the ozonated bath for between approximately 30 seconds and 5 minutes. The substrates are rinsed with a DI water and ozone rinse after being removed from the bath. Removal of an oxide layer is performed by acid etching the substrate with an acid etch solution. The acid etching solution may, for example, comprise water, hydrofluoric acid (HF) and tetramethylammonium hydroxide (TMAH) in an approximate ratio of 100:1:6, respectively. The substrate is then rinsed in a cascade overflow of DI water for approximately 5 minutes. Etching of the polysilicon is then performed with a solution consisting, for example, of approximately 2.25% of TMAH for approximately 5 minutes at 30° C. The substrate is again rinsed in a cascade overflow of DI water for approximately 5 minutes, followed by a mechanical scrub.
REFERENCES:
patent: 4579760 (1986-04-01), Hause et al.
patent: 4996082 (1991-02-01), Guckel et al.
patent: 5454901 (1995-10-01), Tsuji
patent: 5464480 (1995-11-01), Matthews
patent: 5626681 (1997-05-01), Nakano et al.
patent: 5803980 (1998-09-01), Pas et al.
patent: 5837662 (1998-11-01), Chai et al.
patent: 6100198 (2000-08-01), Grieger et al.
patent: 6310018 (2001-10-01), Behr et al.
patent: 6314679 (1994-11-01), None
patent: 8264399 (1996-10-01), None
Kashiwagi, The semiconductor wafer washing —by using ozone containing pure water to oxidise water surface and incorporate metallic impuriites, the etching away oxide layer with impurities using diluted hydrofluroic acid, (English Abstract of JP 6314679 , Nov. 1994.*
Saga et al., Preservation of semiconductor substrate and manufacture of semiconductor device, (English abstract and constitution of JP 8264399 A), Oct. 1996.*
Wolf, Stanley, Ph.D. and Tauber, Richard N., Ph.D., “Wet Processing: Cleaning, Etching, and Liftoff” Silicone Processing for the VLSI Era, vol. 1, Process Tehcnology, Lattice Press, 15:514-520, 1986.
Barnhart Gunnar A.
Grieger Eric K.
Kennedy Tim J.
Whitney Robert H.
Umez-Eronini Lynette T.
Utech Benjamin L.
LandOfFree
Post-planarization, pre-oxide removal ozone treatment does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Post-planarization, pre-oxide removal ozone treatment, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Post-planarization, pre-oxide removal ozone treatment will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3149303