Post-package trimming of analog integrated circuits

Details Post-package trimming of analog integrated circuits Post-package trimming of analog integrated circuits

2001-08-09

2003-09-16

Cuneo, Kamand (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S1540PB, C365S042000

Reexamination Certificate

active

06621284

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to precision trimming of analog integrated circuits (ICs) after packaging and in particular to trimming linear voltage regulators after packaging.
BACKGROUND
Analog integrated circuits (ICs), including linear voltage regulators, often require precision trimming after fabrication. Trimming generally involves changing resistance values to change voltage or current levels. For example, trimming is often performed to cancel process variation among wafers, since voltage tolerances on the order of +/−0.5% are required of today's technologies. Alternatively, multiple options (e.g., voltage levels output by a linear regulator) may be fabricated into a single IC, where one such option must be chosen based on a given customer's requirements. Selection of the desired option for each customer is accomplished by trimming. Trimming allows batch processing of many ICs at once, using a single fabrication process, with customization performed toward the end of the fabrication process.
Typical methods of trimming include blowing fuseable links, burning zener diodes, and laser trimming resistors. Trimming is usually performed on each die at the wafer level, during wafer sort, before the die are packaged. The main function of the wafer sort step, in addition to trimming, is to identify working die for packaging.
Trimming analog ICs at the wafer level has several disadvantages. First, it can be expensive and time consuming. If a product has a high yield, it is desirable to forego wafer sort and proceed directly to packaging to save the cost and time of wafer sort. However, the necessity of trimming precludes this. Second, trimming at the wafer level often results in package shift. Package shift occurs when the value of the trimmed parameter shifts when the die is packaged. Accordingly, an improved, more reliable trimming technique is desirable.
SUMMARY
In accordance with the present invention, a circuit arrangement is used for post-package trimming of an analog integrated circuit, such as a five-pin linear regulator. The circuit arrangement and the analog integrated circuit may be included in a single package. The circuit arrangement includes a test mode input circuit configured to identify a test mode operation and to generate a test mode signal. A register control circuit is coupled to the test mode input circuit and configured to generate a data signal and a plurality of control signals during the test mode operation. A register circuit includes at least one bit circuit including a storage device and a shift register bit latch. The register circuit is coupled to the register control circuit to receive the data signal and the control signals. The register circuit is configured to supply the data signal and the control signals to the at least one bit circuit to program the storage device and to generate a plurality of trim control signals. A program voltage sense circuit is coupled to the register circuit and configured to sense a program voltage. A trim control circuit is coupled to the register circuit and configured to apply the trim control signals.
In an exemplary method of trimming an analog integrated circuit (e.g., a five-pin linear regulator) after packaging, a packaged integrated circuit is provided, and a test mode operation of the packaged integrated circuit is established. A plurality of input data is received during the test mode operation. A plurality of storage devices is programmed, based on the input data. A plurality of trim control signals is generated, based on the states of the storage devices. The trim control signals are applied to modify a normal operation of the packaged integrated circuit.
This post-package trimming technique has several advantages. First, by skipping the wafer sort step, the time and cost of wafer sorting are saved. Second, package shift of the parameters of trimmed die is avoided since the die are trimmed after they are packaged. Third, product delivery to customers is faster since packages need only be marked and tested upon receipt of an order, rather than trimmed, sorted, packaged, marked, and tested, all of which add up to a time consuming process. The post-package trimming technique offers customers faster delivery of a more reliable product.


REFERENCES:
patent: 5263031 (1993-11-01), Inoue
patent: 6240033 (2001-05-01), Yang et al.

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