Metal treatment – Stock – Ferrous
Patent
1978-06-05
1986-05-27
Larkins, William D.
Metal treatment
Stock
Ferrous
148 15, 29571, 29578, 357 45, 357 91, H01L 2978, H01L 2704, G11C 1140
Patent
active
045918910
ABSTRACT:
A MOS read only memory, or ROM, is formed by a process compatible with standard P-channel or N-channel metal or silicon gate manufacturing methods. The ROM is programmed either after the protective nitride layer has been applied and patterned, usually the last step in the slice processing method before electrical testing of the devices, or after the electrical testing of the devices. All potential MOS transistors in the ROM array are initially at a logic "0" or a logic "1". An electron beam slice printing machine is used to program the selected transistors in the ROM array to change their logic state by exposing the gates of the selected transistors to an electron beam. The gates to be exposed are predetermined by a coding on a magnetic tape which corresponds to the desired ROM code. No electron beam mask is necessary since the beam only exposes in selected areas.
REFERENCES:
patent: 3688389 (1972-09-01), Nakanuma
patent: 3865651 (1975-02-01), Arita
patent: 3914855 (1975-10-01), Cheney
patent: 4129936 (1979-12-01), Takei
Chatterjee Pallab K.
Tasch, Jr. Al F.
Graham John G.
Groover III Robert
Larkins William D.
Sorensen Douglas A.
Texas Instruments Incorporated
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