Post last wiring level inductor using patterned plate process

Details Post last wiring level inductor using patterned plate process Post last wiring level inductor using patterned plate process

2008-07-10

2010-06-08

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Making passive device

C438S622000, C257SE21022

Reexamination Certificate

active

07732295

ABSTRACT:
A method of forming a semiconductor substrate. A substrate is provided. At least one metal wiring level is within the substrate. A first insulative layer is deposited on a surface of the substrate. A portion of a wire bond pad is formed within the first insulative layer. A second insulative layer is deposited on the first insulative layer. An inductor is within the second insulative layer using a patterned plate process. A remaining portion of the wire bond pad is formed within the second insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor.

REFERENCES:
patent: 5478773 (1995-12-01), Dow et al.
patent: 5874883 (1999-02-01), Uemura et al.
patent: 5917244 (1999-06-01), Lee et al.
patent: 6101371 (2000-08-01), Barber et al.
patent: 6163957 (2000-12-01), Jiang et al.
patent: 6259160 (2001-07-01), Lopatin et al.
patent: 6292086 (2001-09-01), Chu
patent: 6319827 (2001-11-01), Kowalski et al.
patent: 6387747 (2002-05-01), Cha et al.
patent: 6472721 (2002-10-01), Ma et al.
patent: 6518165 (2003-02-01), Yoon et al.
patent: 6534374 (2003-03-01), Johnson et al.
patent: 6582989 (2003-06-01), Biegelsen et al.
patent: 6646534 (2003-11-01), Ahn et al.
patent: 6664882 (2003-12-01), Andoh et al.
patent: 6714112 (2004-03-01), Beng et al.
patent: 6727154 (2004-04-01), Gardner
patent: 6730982 (2004-05-01), Barth et al.
patent: 6869870 (2005-03-01), Lin
patent: 7207096 (2007-04-01), Gambino et al.
patent: 7319049 (2008-01-01), Oi et al.
patent: 2002/0056888 (2002-05-01), Depetro
patent: 2003/0001712 (2003-01-01), Zou et al.
patent: 2003/0076209 (2003-04-01), Tsai et al.
patent: 2003/0077845 (2003-04-01), Ohkubo et al.
patent: 2003/0179064 (2003-09-01), Chua et al.
patent: 2004/0004266 (2004-01-01), Furumiya et al.
patent: 2004/0157370 (2004-08-01), Gardner
patent: 2004/0195652 (2004-10-01), Okada
patent: 2004/0217443 (2004-11-01), Davies
patent: 2004/0217840 (2004-11-01), Lee et al.
patent: 2005/0167780 (2005-08-01), Edelstein et al.
patent: 2232962 (1990-09-01), None
patent: 4280407 (1992-10-01), None
patent: 2000232202 (2000-08-01), None
Notice of Allowance (Mail Date Apr. 1, 2009) for U.S. Appl. No. 12/174,047, filed Jul. 16, 2008.
Meyer et al.; Si IC-Compatible Inductors and LC Passive Filters; IEEE Journal of Solid-State Circuits, vol. 25, No. 4, Aug. 1990; pp. 1028-1031.
Office Action (Mail Date Jun. 24, 2009) for U.S. Appl. No. 12/174,020, filed Jul. 16, 2008.
Office Action (Mail Date Nov. 20, 2009) for U.S. Appl. No. 12/170,489, filed Jul. 10, 2008.
Office Action (Mail Date Dec. 11, 2009) for U.S. Appl. No. 12/174,020, filed Jul. 16, 2008.
Office Action (Mail Date Aug. 19, 2009) for U.S. Appl. No. 12/170,464, filed Jul. 10, 2008.

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