Post high voltage gate dielectric pattern plasma surface...

Details Post high voltage gate dielectric pattern plasma surface... Post high voltage gate dielectric pattern plasma surface...

2006-05-23

2006-05-23

Norton, Nadine G. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S275000

Reexamination Certificate

active

07049242

ABSTRACT:
The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer. The method further includes subjecting the exposed nitridated, high voltage dielectric to a plasma to remove the accelerant residue.

REFERENCES:
patent: 2004/0067619 (2004-04-01), Niimi et al.

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