Post-etch treatment of a semiconductor device

Details Post-etch treatment of a semiconductor device Post-etch treatment of a semiconductor device

1999-06-17

2001-04-17

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S720000, C438S721000

Reexamination Certificate

active

06218311

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates generally to electronic devices, and more particularly to post-etch treatment of a semiconductor device.
BACKGROUND OF THE INVENTION
Modern electronic equipment such as televisions, telephones, radios and computers are generally constructed of solid state devices. Solid state devices are preferred in electronic equipment because they are extremely small and relatively inexpensive. Additionally, solid state devices are very reliable because they have no moving parts, but are based on the movement of charge carriers.
Solid state devices may be transistors, capacitors, resistors and the like. These devices are fabricated on a substrate and interconnected to form integrated circuits. Device fabrication typically includes depositing, patterning and etching conductor, semiconductor and insulator layers that make up features of the device.
Etching of metal and poly-metal gate structures is known to damage the underlying gate oxide, degrading its integrity and leading to device failure. To restore gate oxide integrity (GOI), post-gate-etch oxidation processes have been used. These processes, however, can oxidize the metal and poly-metal gate structures, resulting in high sheet resistance. To prevent gate oxidation, a selective oxidation process that uses N
2
diluted in H
2
/H
2
0
ambient has been proposed. Selective oxidation is unproven for use in large scale manufacturing and impractical because of the difficulty in achieving sufficient oxidation at the bottom of the gate to remove etch damage while preventing the gate from oxidizing.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method for post-etch treatment of an etch-damaged semiconductor device is provided that substantially eliminates or reduces disadvantages and problems associated with previously developed methods. In particular, the present invention uses a protective cover to inhibit or prevent detrimental oxidation of the semiconductor device during a post-gate-etch oxidation process to repair etch damage to the device.
In one embodiment of the present invention, post-etch treatment of an etch-damaged semiconductor device includes forming a protective cover outwardly of an oxidizable section of the device. The protective cover is operable to at least inhibit oxidation of the section. While the oxidizable section is covered, an oxide structure is formed. The oxide structure is operable to at least ameliorate etch damage to the semiconductor device.
More specifically, in a particular embodiment, the semiconductor device may be a metal oxide semiconductor (MOS) device including a gate electrode having an oxidizable section and a gate oxide having an etch-damaged section. In this embodiment, the protective cover may be formed from a nitride layer outwardly of the gate electrode and the gate oxide. The protective cover is formed by etching the nitride layer until at least part of the etch-damaged section is exposed or removed. The oxide structure may be formed from part of a second oxide layer that is grown or deposited during a post-gate-etch oxidation process.
Technical advantages of the present invention include providing an improved method for post-etch treatment of a semiconductor device. In particular, an oxidizable section of the device is covered during a post-etch oxidation process to repair etch damage to the device. The cover inhibits or prevents detrimental oxidation of the oxidizable layer that can adversely affect the device. Accordingly, metal oxide semiconductor (MOS) or other devices having an oxidizable section may be manufactured with high oxide integrity and low sheet resistance. In addition, the method may be used in large scale device manufacturing.


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Wolf et al.; Silicon Processing for the VLSI Era; vol. 1, p. 534, 1986.

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