Positive gate stress during erase to improve retention in...

Details Positive gate stress during erase to improve retention in... Positive gate stress during erase to improve retention in...

2006-11-28

2006-11-28

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185030, C365S185020

Reexamination Certificate

active

07142455

ABSTRACT:
A new method for improving the accuracy of read-write operations in a multi-level flash memory cell is disclosed. The method reduces the read margin disturbance caused by the accumulation of holes at a tunneling oxide or tunneling oxide-silicon interface underneath a floating gate of the cell by applying a positive stress to the word line after a program-erase cycle.

REFERENCES:
patent: 6049484 (2000-04-01), Lee et al.
patent: 6614693 (2003-09-01), Lee et al.
patent: 6700820 (2004-03-01), Elmhurst et al.
patent: 2005/0179079 (2005-08-01), Wu

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