Positive edge triggered flip flop

Details Positive edge triggered flip flop Positive edge triggered flip flop

1996-08-21

1998-07-14

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327202, 327218, H03K 3037

Patent

active

057810532

ABSTRACT:
A positive edge triggered flip flop which includes a master stage and a slave stage. The master stage includes an inverter that receives a clock input (C), and a first NAND gate having one input port for receiving a data input (D). The master stage also includes a second NAND gate and a first NOR gate that have their respective output connected to an input port of the other gate. The slave stage receives an inverted clock output from the inverter of the master stage. The slave stage includes a third NAND gate and a second NOR gate that also have their respective output connected to an input port of the other gate. An output value (Y) is read from the output of the second NOR gate.

REFERENCES:
patent: 4855617 (1989-08-01), Ovens
patent: 4893028 (1990-01-01), Beltramini
patent: 5051610 (1991-09-01), Terane et al.
patent: 5200649 (1993-04-01), Fukui
Schilling et al., "Electronic Circuits, Discrete and Integrated", 3rd ed., pp. 547-549, 1989.
Thomas McCalla, Digital Logic and Computer Design, 1992, pp. 261-291.
P. Vignron, Coherent Design of Asynchronous Circuits, Published in IEE Proceedings E (Computers and Digital Techniques), vol. 130, Part E, No. 6, pp. 190-202, Nov. 1983.

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