Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
2000-01-18
2002-04-23
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
C257S758000, C438S401000, C438S462000, C438S975000
Reexamination Certificate
active
06376924
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to an improvement in alignment of semiconductor device formed by overlaying a plurality of layers.
2. Description of the Background Art
Recently, with high integration of elements, the design rule becomes smaller and a manufacturing process becomes more complicated with planarization technique and use of new materials. Since miniaturization of contact holes and interconnections requires higher precision in alignment of the contact holes and the interconnections and therefore a higher alignment technique is needed.
To form contact holes and interconnections, an exposure device termed a stepper is used. A mask pattern projected by reducing projection lens system is repeatedly exposed while moving in an XY direction, to form a plurality of circuit patterns on a whole surface of a semiconductor substrate.
FIG. 41
schematically shows an operation of the stepper in a lithography process. As shown in
FIG. 41
, a plurality of exposure regions ER each of which is projected by one exposure are formed on a whole surface of a semiconductor substrate SB. A plurality of exposures are made on each exposure region ER, overlaying different patterns, to form a semiconductor device.
In overlay of patterns, an alignment mark for alignment is needed and after overlay, an overlay check mark is needed to check if the overlay is made properly. Each exposure region ER is provided with these marks.
In general, most part of the exposure region is an element formation region in which a plurality of semiconductor elements are formed and the rest blank part is used for forming the alignment mark and the overlay check mark.
FIG. 42
shows a schematic structure of the exposure region ER. In
FIG. 42
, two element formation regions SR are placed at an interval and an overlay check mark OLM
1
and an alignment mark ALM
1
are provided in a blank portion BR between the two element formation regions SR and overlay check marks OLM
2
to OLM
5
are provided in the four corners of a blank portion BR surrounding the two element formation regions SR. Further, between the overlay check mark OLM
2
and OLM
3
provided is an alignment mark ALM
2
.
Though the five overlay check marks and the two alignment marks are shown in
FIG. 42
, the number of either mark is not limited to the above numbers. Further, since the present invention can be applied to both the alignment mark and the overlay check mark, the alignment mark and the overlay check mark are not distinguished from each other and both marks are generally referred to as position check mark in the discussion hereinafter (including discussion of the preferred embodiment of the invention).
FIG. 43
is a plan view of a position check mark MK
1
as an example of position check mark. As shown in
FIG. 43
, the position check mark MK
1
consists of a plurality of mark structures
10
which are each of elongated shape having a predetermined length and arranged in parallel at intervals.
FIG. 44
is a cross sectional view taken along the line A—A of FIG.
43
. As shown in
FIG. 44
, the mark structure
10
consists of a gate oxide film
102
(a thermal oxide film having a thickness of about 10 nm) formed on a silicon substrate
101
, a gate wiring layer
103
formed on the gate oxide film
102
, an insulating film
104
formed on the gate wiring layer
103
and a sidewall
105
formed in contact with side surfaces of the insulating film
104
, the gate wiring layer
103
and the gate oxide film
102
.
The gate wiring layer
103
is a polycide consisting of two layers, i.e., a doped polysilicon layer
1031
having a thickness of, e.g., 100 nm and a tungsten silicide (WSi) layer
1032
having a thickness of 100 nm. The insulating film
104
is made of a TEOS (Tetra Ethyl Orthosilicate) oxide film having a thickness of, e.g., about 200 nm, and the sidewall
105
is made of a TEOS oxide film having a thickness of, e.g., 50 nm.
A stopper insulating film
106
is so provided as to cover an arrangement of mark structures
10
each having the above structure. The stopper insulating film
106
is a translucent silicon nitride film having a thickness of 50 nm. An interlayer insulating film
107
is formed of a TEOS oxide film having a thickness of e.g., 500 nm, covering the stopper insulating film
106
, and its outermost surface is planarized by CMP (Chemical Mechanical Polishing).
On the interlayer insulating film
107
, an opaque bit line layer
109
is formed as a polycide of a doped polysilicon layer
1091
having a thickness of, e.g., 100 nm and a tungsten silicide (WSi) layer
1092
having a thickness of 100 nm.
A mark structure
10
substantially has the same structure as a gate of a MOS transistor, for it is formed through the same process steps as the gate of the MOS transistor when the MOS transistor is formed as one of semiconductor elements in the element formation region SR of
FIG. 42
, and this is a technique for preventing an increase in the number of process steps by steps dedicated to formation of the position check mark MK
1
. Therefore, the mark structure
10
is a dummy gate and has no function of gate.
The stopper insulating film
106
serves as an etching stopper in formation of the contact hole penetrating the interlayer insulating film
107
to reach the semiconductor substrate
101
in the element formation region SR in a self-align manner, and is also provided in formation of the MOS transistor in the element formation region SR.
The interlayer insulating film
107
is also formed in the element formation region SR, and on the interlayer insulating film
107
planarized by CMP, the bit line layer
109
is formed.
Thus, since the mark structure
10
is formed in the same manner as the gate of the MOS transistor and on the mark structure
10
, the opaque bit line layer
109
is formed with the planarized interlayer insulating film
107
interposed therebetween, the following problem arises.
When the bit line layer
109
is patterned to form a predetermined bit-line pattern, a mask pattern of the stepper is aligned by using the position check mark MK
1
consisting of the mark structures
10
. After the bit-line pattern is formed, the position check mark MK
1
is used to check if the pattern is overlaid on a proper position. In both cases, since the mark structures
10
are measured through the opaque bit line layer
109
and the bit line layer
109
hardly transmits the visible light used in the measurement, the level difference of the mark structure
10
can hardly be measured. Further, since the interlayer insulating film
107
is planarized, disadvantageously, the existences of the mark structures
10
can not be seen from the interlayer insulating film
107
.
Furthermore, affected by the translucent stopper insulating film
106
, the intensity of the visible light used for the measurement is lowered and the contrast is worsened, disadvantageously not to allow a measurement with high precision.
Though the position check mark MK
1
consisting of arranged mark structures
10
each of which substantially has the same structure as the gate of the MOS transistor has been discussed above, the structure of the mark structure is not limited to the gate structure.
FIG. 45
is a plan view of a position check mark MK
2
as an example of a mark. As shown in
FIG. 45
, the position check mark MK
2
consists of elongated openings having a predetermined length arranged in parallel at intervals on an oxide film
734
.
FIG. 46
is a cross sectional view taken along the line B—B of FIG.
45
. As shown in
FIG. 46
, the position check mark MK
2
consists of openings OP where an interlayer insulating film
717
formed on the silicon substrate
101
is selectively removed in a rectangular shape to partially expose the silicon substrate
101
and a doped polysilicon layer
733
buried in the openings OP, having a thickness of 50 nm, and the oxide film
734
formed on the doped polysilicon layer
733
. Fur
Tomita Kazuo
Ueno Atsushi
Loke Steven
Mitsubishi Denki & Kabushiki Kaisha
Owens Douglas W.
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