Portable minicomputer for testing memories

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364900, G06F 1116

Patent

active

045596263

ABSTRACT:
A portable high speed minicomputer tester is disclosed for isolating failures in a random access memory. The device includes a central processing unit having an address counter and means for generating a plurality of test words. Individual test words are generated automatically and stored in both an internal memory and the memory under test. At a predetermined address, a test word is read out of the memories and compared. If there are any discrepancies, the minicomputer sets a latch corresponding to the failed test word bit and identifies the failed bit on a digital display readout. Using fault conversion tables, an operator can trace a discrepancy to the bit location of a memory chip in the memory under test.

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Anolick et al., "Memory Test System", IBM Tech. Disclosure Bulletin, vol. 22, No. 7, (Dec. 1979).
Hollands, et al., "Memory Tester Using Random Addresses and Random Data," IBM Tech. Disclosure Bulletin, vol. 23, No. 1, (Jun. 1980).

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