Porous silicon undercut etching deterrent masks and related...

Details Porous silicon undercut etching deterrent masks and related... Porous silicon undercut etching deterrent masks and related...

2007-04-17

2007-04-17

Smith, Zandra V. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S537000, C257S751000, C438S597000, C438S586000

Reexamination Certificate

active

11242237

ABSTRACT:
The disclosed invention relates to masked silicon structures and methods for making porous silicon in selected areas of a silicon substrate via anodic etching. The masked silicon structures comprise: (1) a frontside barrier layer; and (2) a backside opaque ohmic contact layer. The frontside barrier layer includes a plurality of discrete barrier openings bounded by a contiguous frontside portion of the barrier layer, thereby defining a first aperture having a first shape and a first center point. The backside opaque ohmic contact layer includes a second aperture bounded by a contiguous backside portion of the ohmic contact layer, thereby defining a second aperture having a second shape and a second center point. The first and second center points share a perpendicular axis. The first shape is substantially the same as the second shape but slightly larger, and is trans-concentrically positioned relative to the second shape about the shared axis.

REFERENCES:
patent: 4931845 (1990-06-01), Ema
patent: 4985750 (1991-01-01), Hoshino
patent: 5525837 (1996-06-01), Choudhury
patent: 5614437 (1997-03-01), Choudhury
patent: 2003/0132496 (2003-07-01), Terano et al.

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