Porous insulator for line-to-line capacitance reduction

Details Porous insulator for line-to-line capacitance reduction Porous insulator for line-to-line capacitance reduction

1995-05-23

1996-08-20

Brown, Peter Toby

Active solid-state devices (e.g., transistors, solid-state diode

With means to control surface effects

Insulating coating

257637, 257644, 257758, 257760, H01L 21316, H01L 23522

Patent

active

055481590

ABSTRACT:
An interconnect structure and method is described herein. First, interconnect lines 14a-d are formed on a semiconductor body 10. Then, a dielectric layer 20 is coated over the semiconductor body and the interconnect lines 14a-d to a thickness sufficient to more than fill the gaps between adjacent interconnect lines. The dielectric layer 20 is baked and then cured at a elevated temperature greater than the baking temperature. By using baking, then curing, the dielectric layer 20 inside the gaps has a lower density than that above interconnect lines and that in open fields. The removal of dielectric layer from the top of the interconnect lines by etchback is optional. Finally, a layer of silicon dioxide 12 is deposited over the interconnect lines 14a-d and the dielectric layer 20. In one embodiment, contact vias 11 are then etched through the silicon dioxide 12 and dielectric layer 20 to the interconnect lines 14a-c. Preferably, the dielectric material is spun on. One advantage of the invention is providing a metallization scheme that reduces line-to-line capacitance. A further advantage of the invention is providing a metallization scheme that reduces crosstalk and power dissipation. A further advantage of the invention is providing a dielectric layer between interconnect lines having a lower density and a lower dielectric constant than dense silicon dioxide.

REFERENCES:
patent: 4981830 (1991-01-01), Clodgo et al.
patent: 5155576 (1992-10-01), Mizushima
Translation of Japan Kokai Publication #63-0179548 12 pages.

Affiliated with

Also associated with

Rating

Porous insulator for line-to-line capacitance reduction does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Porous insulator for line-to-line capacitance reduction, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Porous insulator for line-to-line capacitance reduction will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2332220