Porous circuit macro for semiconductor integrated circuits

Details Porous circuit macro for semiconductor integrated circuits Porous circuit macro for semiconductor integrated circuits

1989-02-23

1990-03-20

Mintel, William

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 71, 357 41, 357 45, 357 68, 36523001, 36518901, H01L 2702

Patent

active

049105744

ABSTRACT:
A circuit macro is provided for a VLSI circuit device having a semiconductor substrate and M1 and M2 metal layers defining a grid of M1 and M2 conductive lines extending in orthogonal directions. Numerous similar unit cells are arrayed side-by-side in rows extending in one direction and each unit cell spans an integral number of M1 conductive lines and an integral number of M2 conductive lines. The circuit device includes a plurality of circuit blocks each including two of the rows of unit cells. A plurality of wiring bays extend between adjacent circuit blocks, and each wiring bay includes a plurality of M1 conductive lines. The circuit macro includes a number of circuti blocks separated by wiring bays, and connections extend to unit cells of circuit blocks included in the macro. Both M1 and M2 conductive lines are used for connections in the macro, and additional M1 and M2 conductive lines, including M1 connductive lines in the wiring bays, extend uninterrupted across the macro providing a porous yet dense macro and facilitating macro placement and wiring.

REFERENCES:
patent: 4021838 (1977-05-01), Warwick
patent: 4568961 (1986-02-01), Noto
patent: 4596003 (1986-06-01), Shimizu
patent: 4677592 (1987-06-01), Sakurai et al.
patent: 4688070 (1987-08-01), Shiotari et al.
patent: 4731643 (1988-03-01), Dunham et al.
patent: 4731761 (1988-03-01), Kobayashi
patent: 4742383 (1988-05-01), Fitzgerald
patent: 4811073 (1989-03-01), Kitamura et al.

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