Porous ceramics and method of preparing the same as well as...

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Reexamination Certificate

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C428S209000, C174S258000

Reexamination Certificate

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06800360

ABSTRACT:

TECHNICAL FIELD
The present invention relates to porous ceramics and a method of preparing the same, and more specifically, it relates to porous ceramics for serving as an electrical insulating material applied to various types of wiring circuit boards or a lightweight structural material having moisture absorption resistance.
The present invention also relates to a microstrip substrate employed for forming a waveguide of a high frequency of at least 1 GHz, particularly at least 30 GHz, and more specifically, it relates to a microstrip substrate having a microstrip line consisting of a conductor formed on the surface of a substrate consisting of porous ceramics.
BACKGROUND ART
Improvements of characteristics such as further weight saving and improvement in strength or improvements of electrical characteristics are recently required to ceramics employed as various structural materials or electronic component materials. In a wafer transfer stage or a plotting stage used as a component of semiconductor equipment, for example, further weight saving of a stage material is required for high precision and high-speed driving. As to a circuit board or an insulating material employed for an electronic apparatus, a material having lower permittivity and lower dielectric loss is strongly required following recent improvement in frequency.
Therefore, it is conceivably effective to use ceramics in a porous state. When the relative density of ceramics is reduced to 50%, for example, the weight thereof can be reduced to 50%. Further, the air exhibits excellent electrical insulation properties with permittivity of about 1 and dielectric loss of zero, and hence porous ceramics attains desirable characteristics as a material to which low permittivity and low dielectric loss are required.
However, it is difficult to obtain a porous sintered body containing homogeneously dispersed fine pores simply by controlling a sintering step for a ceramic sintered body. In general, coarse pores are formed to disadvantageously reduce strength or result in heterogeneous characteristics. Further, most of pores forming the obtained porous sintered body are open pores deteriorating humidity resistance intrinsic to the ceramics, and desired characteristics cannot be attained in view of practicality due to remarkable deterioration of electrical characteristics (permittivity and dielectric loss) resulting from moisture, dispersion of various characteristics or the like.
Therefore, various methods are devised for obtaining a porous material consisting of fine closed pores. For example, Japanese Patent Laying-Open No. 3-177372 discloses an SiC-based porous sintered body containing a phase having a different thermal expansion coefficient to exhibit a total volume ratio of closed pores of 0.07 to 27.5%, in order to improve toughness. When this method is employed for obtaining an SiC-based porous sintered body having closed pores in a ratio of at least 27.5%, however, oxidation resistance is reduced or the pore sizes are increased.
Japanese Patent Laying-Open No. 5-310469.discloses a high-purity calcia sintered body exhibiting a ratio of 5 to 15% as to closed pores of 2 to 10 &mgr;m in diameter. This gazette states that this sintered body is obtained by mixing a foaming agent such as phenol aldehyde or flammable fine powder such as carbon black into muddy serosity of calcium carbonate and water and calcining the mixture. According to this method, however, residues of the foaming agent or the flammable fine powder remain in the closed pores while it is difficult to hold the shape if the amount of the foaming agent is increased, and hence the closed pore ratio cannot be increased.
Japanese Patent Laying-Open No. 6-157157 discloses lightweight and high-strength ceramics formed with closed pores prepared by equilibrating the pressure of the closed pores in the ceramics and the pressure in a calcinator. In this method, however, it is difficult to control the pore size.
According to Japanese Patent Laying-Open No. 11-116333, porous glass having closed pores of nanometer order is adjusted by phase-splitting borosilicate glass by heat treatment, eluting a soluble phase, performing pulverization and thereafter melting only the surface with a flame for forming closed pores. This gazette discloses a method of adjusting a mixture of glass, an aggregate and resin balls with a porous aggregate obtained by crystallizing/heat-treating the glass for preparing a ceramic circuit board by green sheet lamination. The ceramic circuit board obtained by this method exhibits relative permittivity of not more than 2 and a thermal expansion coefficient of 13 to 17 ppm/° C. This method is restricted to a material phase-split by heat treatment for eluting a soluble phase. Further, not only the process is complicated but also composition with a different phase is necessary, and hence intrinsic mechanical and electrical characteristics cannot be obtained. When open pores are temporarily exposed to the atmosphere to cause adsorption of moisture or the like, further, it is difficult to completely dissociate and control this.
In the aforementioned prior art forming closed pores, a second phase, such as a foaming agent, a melt or a phase having a different thermal expansion coefficient, different from the matrix phase must be added and hence electrical and mechanical characteristics are remarkably reduced due to the second phase or residues of the second phase. Further, the ratio and the size of formable pores are limited such that no matrix skeleton can be formed or the pore size cannot be controlled if the porosity is increased.
Porous ceramics, having excellent characteristics such as a light weight, heat insulating properties, excellent workability, high dimensional accuracy (fow shrinkage factor) in calcination, low permittivity and the like, can be expected for application to various structural materials, members for a filter and a vacuum chuck and electronic materials such as an insulating member (substrate), a low dielectric loss member (substrate) and the like.
However, porous ceramics having an irregular surface resulting from pores is insufficient in surface accuracy, and inferior in abrasion resistance and frictional characteristics or adhesion, flatness, film density (pinholes), dimensional accuracy and humidity resistance in a case of forming a functional thin film or a conductive pattern on the surface in application to the aforementioned usage.
As a method of smoothing the porous surface, therefore, there has been reported a method of grinding/polishing the surface similarly to dense ceramics or a method of impregnating the surface of a porous material with a ceramic slurry and thereafter sintering the same for densifying the surface (Japanese Patent Laying-Open No. 61-53146,Japanese Patent Laying-Open No. 1-164783, Japanese Patent Laying-Open No. 1-215778 or Japanese Patent Publication No. 1-47435).
When merely working the material by a method similar to that for a dense body, however, it is difficult to obtain a smooth surface of sub-micron order due to remaining irregularity resulting from pores. When ceramics or glass grains are simply deposited on the surface of porous ceramics, it is difficult to obtain a sufficiently flat surface, and reliability is deteriorated due to falling of the deposited grains or the like.
When a dense ceramic sheet is stacked on the surface of a porous material or the porous material is impregnated with a dense ceramic slurry and calcined, stress is caused in a dense region of the ceramics and the porous region due to a large shrinkage factor of the dense ceramic part, and hence the matrix is deformed (warped), a target dense layer is not formed or readily separated, or sufficient smoothness cannot be attained. The number of steps in the fabrication process is increased, to result in inferior productivity or the like.
As a conventional high-frequency circuit board, a dielectric substrate is employed as a relay substrate for connecting a package and an integrated circuit (IC) with each other or a substrate fo

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