Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Reexamination Certificate
2000-11-27
2003-09-02
Eckert, George (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
C257S066000, C257S070000, C257S623000
Reexamination Certificate
active
06614054
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a thin film transistor (TFT) of the type used in a liquid crystal display (LCD). More particularly, it relates to a polycrystalline silicon thin film transistor (Poly-Si TFT) and a method of manufacturing the same.
2. Discussion of the Related Art
Generally, in order to form a polycrystalline silicon membrane, intrinsic amorphous silicon is first deposited by conventional methods, for example, Plasma Chemical Vapor Deposition (PCVD) or Low Pressure CVD (LPCVD). Then that amorphous silicon is crystallized. The crystallization methods can be classified into three types.
Firstly, a metal induced crystallization (MIC) technique. The MIC technique can use large size glass substrates, since the MIC technique can use a low crystallization temperature.
Secondly, a solid phase crystallization (SPC) technique. SPC changes amorphous silicon into polycrystalline silicon by heat-treatment at a high temperature for a long time. It requires forming a buffer layer on a quartz substrate in order to prevent the quartz substrate from diffusing an impurity material. The amorphous silicon layer is then deposited on the buffer layer and crystallized by the heat-treatment.
Thirdly, a laser annealing technique grows polycrystalline silicon using laser irradiation while heating a substrate having an amorphous silicon membrane.
Although metal induced crystallization (MIC) can form polycrystalline silicon on large sized glass substrates, the quality of the resulting membrane is questionable due to the high possibility of residual metallic material in the grain boundaries of the polycrystalline silicon.
The solid phase crystallization (SPC) method results in irregular grain boundaries that cause the gate insulating layer on the polycrystalline silicon layer to grow erratically, leading to a low breakdown voltage. Furthermore, since the grain sizes of the polycrystalline silicon are highly non-uniform, the electrical properties of the resulting device, such as the on-current and the threshold voltage, are not good. Finally, a costly quartz substrate should be employed when performing SPC.
The laser annealing technique is widely used and has been carefully investigated. This method can heat amorphous silicon on a glass substrate up to the melting temperature of the silicon without damaging the substrate.
For a more complete understanding of laser annealing, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
FIGS. 1
a
to
1
d
show the fabrication process steps of a TFT according to the related art. Referring to
FIG. 1
a
, a first insulating layer
2
and an amorphous silicon layer
4
are sequentially formed on a substrate
1
. The first insulating layer
2
prevents the substrate
1
from effusing alkali. The first insulating layer
2
also acts as an antireflection layer that prevents leakage of the excimer-laser beam used in laser annealing.
FIG. 1
b
shows the process step of crystallizing the amorphous silicon layer
4
. An excimer-laser beam quickly heats the amorphous silicon to its melting temperature. If the excimer-laser irradiation stops, the amorphous silicon cools down quickly. Crystal growth of polycrystalline silicon then occurs with the numerous crystal nuclei acting as starting points or “seeds.”
Referring to
FIG. 1
c
, an island-shaped polycrystalline silicon
4
layer is formed by patterning the crystallized poly-silicon. A second insulating material and a first metallic material are deposited sequentially and patterned to form a second insulating layer
6
and a gate electrode
8
. Then, the peripheral portion of the polycrystalline silicon
4
is ion-doped using the gate electrode
8
as a mask.
As shown in
FIG. 1
d
, a third insulating layer
11
is deposited and patterned to form contact holes on the doped portions
12
and
13
. Then, source and drain electrodes
9
and
10
are formed in and around the contact holes.
However, the conventional laser annealing method uses the numerous crystal nuclei as starting points (seeds) at random. The grain size of the polycrystalline silicon is then about 1 &mgr;m. From these results, as shown in
FIG. 2
, many small-sized grains
20
are formed in the channel region of the TFT. This means that the grain boundaries, which affect the electrical properties, are numerous. This deteriorates the electrical properties of the TFT.
Referring to
FIG. 3
, the excimer-laser beam should be irradiated many times to obtain a reliable TFT when large-sized amorphous silicon on a substrate
40
is being crystallized. To accomplish this a second excimer-laser beam
44
can be irradiated over about 90% of the area irradiated by the first excimer-laser. The amorphous silicon is then converted to polycrystalline silicon by repeating the overlap of the laser beams several times.
As the conventional method forms small-sized grains and numerous grain boundaries, it does not produce good electrical properties when the length of TFT channel region is around 10 &mgr;m.
To address these problems, Japanese Journal of Physics (JJAP), pp. 4545-4549, in 1992 and JJAP, pp. 70-74, in 1994 disclose TFTs having a gate electrode with a bridge structure.
FIGS. 4 and 5
explain those techniques.
An insulating layer
52
is formed on a silicon wafer
50
, which has been constructed by removal of the central portion
50
b
of the silicon wafer
50
using preferential etching. Then, amorphous silicon
54
is formed on the insulating layer
52
. That silicon is then crystallized using an excimer-laser. The grain size of the polycrystalline silicon grows up to 50 &mgr;m. In this method, the peripheral portion
50
a
of the silicon wafer
50
acts as the bridge, which supports the central portion
50
b
of the silicon wafer
50
.
FIG. 5
shows a cross sectional view of a TFT that is made of polycrystalline silicon formed using that crystallization method (in FIG.
4
). A gate electrode
56
is formed under the silicon wafer
52
. Patterning yields the polycrystalline silicon active layer
54
. After that, source and drain electrodes
58
and
60
are formed.
The field-effect mobility of a TFT fabricated by the method of
FIGS. 4 and 5
is similar to that of a MOS (metal oxide silicon) transistor made of amorphous silicon.
These techniques, however, do not explain the method of forming the preferable grain size and shape. Furthermore, the method of fabricating plural uniform devices on a large size substrate is not suggested.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method of forming a polycrystalline silicon layer having large-sized grains and a TFT fabricated by that method.
In order to achieve the object of the invention, the present invention provides a method of fabricating a thin film transistor (TFT), including: providing a substrate; depositing amorphous silicon on the substrate; patterning the amorphous silicon to form plural island-shaped amorphous silicon layers, the amorphous silicon layers being parallel to each other; forming etched-spaces between the substrate and the amorphous silicon layers by etching the upper side of the substrate; forming ion stoppers on the corresponding island-shaped amorphous silicon layers; defining channel regions and source and drain ohmic contact regions by doping ions on the island-shaped amorphous silicon layers using the ion stoppers as masks; removing the ion stoppers; forming a first insulating layer covering the amorphous silicon layer; crystallizing the amorphous silicon layers to form polysilicon layers by irradiating laser beams on the first insulating layer; forming a gate electrode on the first insulating layer; forming a second insulating layer covering the gate electrode and the exposed polysilicon layers; patterning the second insulating layer to have contact holes to expose source and drain ohmic contact regions; and forming source and drain electrodes on the second insulating layer, the source and drain electrodes contacting the source and
Eckert George
LG.Philips LCD Co. , Ltd.
McKenna Long & Aldridge LLP
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