Semiconductor device manufacturing: process – Making passive device – Resistor
Reexamination Certificate
2000-05-19
2002-11-05
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Making passive device
Resistor
C438S149000, C438S795000, C438S486000
Reexamination Certificate
active
06475872
ABSTRACT:
CROSS REFERENCE
This application claims the benefit of Korean Patent Application No. 1999-18275, filed on May 20, 1999, under 35 U.S.C. §119, the entirety of which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a thin film transistor (TFT), and more particularly, to a polysilicon thin film transistor (Poly-Si TFT) and a method of manufacturing the same.
2. Description of Related Art
Conventional polysilicon thin film transistors (hereinafter referred to simply as “Poly-Si TFTs” are commonly employed in high-density static random access memory cells (SRAMs) for load pull-up devices, as well as used both as switching elements and as peripheral driver circuitry in large-area active-matrix liquid crystal displays (LCDs).
FIGS. 1A
to
1
D are cross-sectional views illustrating the process of manufacturing a typical Poly-Si TFT of a coplanar type for use in a liquid crystal display device. As shown in
FIG. 1A
, a buffer layer
20
of SiNx or SiOx is formed on a transparent substrate
10
, and an amorphous silicon layer of a thickness of 1500 Å is deposited on the buffer layer
20
. The amorphous silicon layer
20
undergoes the crystallization process so that a polysilicon layer
30
is formed.
As shown in
FIG. 1B
, a gate insulating layer
40
comprising an inorganic insulating material such as SiNx and SiOx, or an organic insulating material such as BCB (benzocyclobutene), and a gate electrode
50
comprising a metal such as Mo, Cr, Al, and Ti are sequentially formed on the polysilicon layer
30
. Then, the substrate
10
having the gate insulating layer
40
and the gate electrode
50
is ion-doped with an n-type impurity or a p-type impurity using the gate electrode
50
as a mask to define source and drain regions
30
b
and
30
c
which are amorphous semiconductor portions.
As shown in
FIG. 1C
, the source and drain regions
30
b
and
30
c
undergo the activation process to active the impurity ion gases using a laser annealing technique or a furnace annealing technique. Sequentially, as shown in
FIG. 1D
, a passivation film
60
comprising an inorganic insulating material, for example, SiNx or SiOx, is formed over the entire substrate
10
while covering the gate electrode
50
. Contact holes
32
and
34
are formed, exposing the source and drain regions
30
b
and
30
c.
Source and drain electrodes
70
and
80
comprising a metal such as Mo and Cr are formed to contact the source and drain regions
30
b
and
30
c
through the contact holes
32
and
34
.
However, the coplanar type Poly-Si TFT having the above-mentioned structure has a problem of degraded electric characteristics during the activation process. First, the conventional process fails to uniformly and densely grow grains crystallized during the activation process of the source and drain regions
30
b
and
30
c.
In other words, in case of the conventional laser annealing technique, the crystallization and activation processes are performed using a laser beam less in energy density than that sufficient to completely melt the amorphous silicon layer, producing grains whose size is thousands of Å to 1 &mgr;m. Thus, defects between grain boundaries degrade the electric characteristics of the TFT.
Secondly, since the gate electrode
50
is made of a metal layer and a temperature of a laser beam during crystallization or activation of the amorphous silicon layer is greater than a melting temperature of the metal layer, a laser beam of a high temperature during crystallization and activation may cause the gate electrode to be molten. Also, if the temperature of a laser beam is set to be lower than the melting temperature of the gate electrode to prevent the gate electrode from being damaged, the crystallization process is not effectively performed, thereby forming incomplete polysilicon layer having amorphous portions.
To overcome these problems, Japanese Patent Publication of Application No. 3-161977 discloses a Poly-Si TFT having a gate electrode comprising an amorphous silicon. According to the above-mentioned patent publication, as shown in
FIG. 2
, the method of manufacturing the prior art TFT comprises the steps of: forming a buffer layer
120
on a substrate
110
; forming a semiconductor layer
130
having a polysilicon layer
130
a
and source and drain regions
130
b
and
130
c;
forming a gate insulating layer
140
and a gate electrode
150
of an amorphous silicon; crystallizing the gate electrode
150
; activating the source and drain regions
130
b
and
130
c
using a laser annealing technique after ion-doping process; and forming a passivation film
160
, source and drain electrodes
170
and
180
.
The prior art TFT described above can have uniform-sized grains being activated using a laser beam having a temperature higher than the melting temperature of a metal. However, in spite of such advantages, in case of using a conventional laser annealing technique or a furnace annealing technique for activation, this process still fails to uniformly and densely grow grains crystallized during the activation process of the source and drain regions
30
b
and
30
c,
thereby deteriorating the electric characteristics of the TFT.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a polysilicon thin film transistor that has good electric characteristics and a low-resistant gate electrode.
In order to achieve the above and other objects, the present invention is directed to a method of manufacturing a thin film transistor for use in a liquid crystal display device, comprising: crystallizing an amorphous silicon layer formed over a substrate using a first SLS (sequential lateral solidification) laser annealing technique to form a polysilicon layer; forming sequentially a gate insulating layer and a gate electrode on the polysilicon layer; ion-doping the polysilicon layer using the gate electrode as a mask to form source and drain regions; and activating the gate electrode and the source and drain regions using a second SLS laser annealing technique.
The present invention further comprises the steps of forming a passivation film on the gate electrode while covering the entire substrate; forming contact holes to expose the source and drain regions; and forming source and drain electrodes to respectively contact the source and drain regions through the contact holes.
The gate electrode comprises an amorphous silicon. A laser beam for use in the SLS laser annealing technique is less than 100 &mgr;m in width.
REFERENCES:
patent: 5807770 (1998-09-01), Mineji
patent: 6159777 (2000-12-01), Takenouchi et al.
patent: 6210996 (2001-04-01), Yamazaki et al.
patent: 6274888 (2001-08-01), Suzuki et al.
patent: 6322625 (2001-11-01), Im
patent: 6323515 (2001-11-01), Yamazaki et al.
patent: 6340830 (2002-01-01), Takemura
patent: 6368945 (2002-04-01), Im
patent: 3161977 (1991-07-01), None
patent: 97/45827 (1997-12-01), None
patent: WO 0171791 (2001-09-01), None
Sposili et al., Single Crystal Si Films via a low-substrate-temperature Excimer-Laser Crystallization Method, 1997,Mat. Res. Soc. Symp. Pro. vol. 452, pp. 953-958.*
James S. IM et al., Appl. Phys. Lett. 70 (25), p. 3434-6 (1997).
J.P. Leonard et al., Mat. Res. Soc. Symp. Proc., vol. 452, pp. 947-952 (1997).
Fujio Okumura et al., Dynamic Leakage Current Reduction Poly-Si TFTs for AMLCDs, pp. 24-27, Functional Devices Research Lab., NEC Corp.
Birch & Stewart Kolasch & Birch, LLP
Everhart Caridad
LG. Philips LCD Co. Ltd.
Luu Chuong A
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