Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2000-09-05
2003-09-30
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S412000, C257S350000, C257S337000, C257S532000, C257S533000, C257S536000
Reexamination Certificate
active
06627971
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit devices and more particularly to the process of manufacture of polysilicon structures with varying values of resistance and the devices produced by the process.
2. Description of Related Art
U.S. Pat. No. 5,705,418 of Liu for “Process for Fabricating Reduced-Thickness High-Resistance Load Resistors in Four-Transistor SRAM Devices” shows a method of forming polysilicon resistors where an oxide layer is used as an Ion Implantation (I/I) block. An oxidation resistant layer is formed and patterned for exposing regions of the polysilicon layer designated for the formation of the load resistors. An oxide layer is formed over the surface of the exposed portions of the polysilicon layer, so that the thickness of the designated regions of the polysilicon layer below the oxide layer is reduced. These designated regions are provided to form load resistors. The oxidation resistant layer is then removed. Then, impurity ions are implanted into exposed regions of the polysilicon layer, not covered by the oxide layer, which are designated for forming interconnectors for the memory cell unit.
U.S. Pat. No. 5,514,617 of Liu for “Method of Making a Variable Resistance Polysilicon Conductor for SRAM Devices” shows how to produce resistors using a patterning method with an I/I (Ion Implantation) process with step areas where variable doping results with higher resistance in the steeper areas than the flat areas, plus heavy doping formed in contact areas by doping through openings in a contact mask.
U.S. Pat. No. 4,643,777 of Maeda for “Method of Manufacturing a Semiconductor Device Comprising Resistors of High and Low Resistances” describes a method of forming resistors in portions of a polysilicon layer with portions covered with a mask and the other portions covered with a molybdenum film. Then the molybdenum film is subjected to a silicifying step. The result is that those regions of the polysilicon film located under the molybdenum film have a low resistance, while the regions of the polysilicon film covered by the mask have a high resistance value.
See U.S. Pat. No. 5,622,884 of Liu for “Method for Manufacturing a Semiconductor Memory Cell and a Polysilicon Load Resistor of the Semiconductor Memory Cell” describe a load resistor formed by depositing a polysilicon layer over an insulating layer. The polysilicon layer is ion implanted with dopant and is then masked and etched to form a high resistance load resistor.
In the past, in order to form polysilicon layers with a different resistance in an integrated circuit, the solution has been to modify the area and length of the polysilicon to meet the criteria required. However, that approach increases the cost of manufacturing due to the complex process.
SUMMARY OF THE INVENTION
In accordance with this invention a device with a plurality of structures with different resistance values includes as follows:
a polysilicon layer upon a substrate,
a hard masking layer formed upon the polysilicon layer,
the hard masking layer including a full thickness portion and a lower thickness portion, and
the polysilicon layer having a high resistance beneath the full thickness portion and a low resistance beneath the low thickness portion.
The hard masking layer is composed of a material selected from the group consisting of silicon oxide and silicon nitride.
The full thickness portion is from about 0.3 &mgr;m to about 0.5 &mgr;m thick, and
the lower thickness portion is from about 0.01 &mgr;m to about 0.15 &mgr;m thick.
The polysilicon layer is formed over a silicon oxide layer selected from a field oxide layer and a gate oxide layer.
REFERENCES:
patent: 4643777 (1987-02-01), Maeda
patent: 5514617 (1996-05-01), Liu
patent: 5622884 (1997-04-01), Liu
patent: 5705418 (1998-01-01), Liu
patent: 1-165156 (1989-06-01), None
patent: 5-109983 (1993-04-01), None
Chen Sen-Fu
Shen Chih-Heng
Wang Huan-Wen
Yen Ying-Tzu
Ackerman Stephen B.
Jones II Graham S.
Saile George O.
Taiwan Semiconductor Manufacturing Company
LandOfFree
Polysilicon structures with different resistance values for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Polysilicon structures with different resistance values for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Polysilicon structures with different resistance values for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3007217