Polysilicon pattern for a floating gate memory

Details Polysilicon pattern for a floating gate memory Polysilicon pattern for a floating gate memory

1987-03-16

1989-05-09

Fears, Terrell W.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 59, 365185, 365 51, H01L 2978, H01L 2904, G11C 502, G11C 1134

Patent

active

048293512

ABSTRACT:
An integrated circuit floating gate memory is formed using two layers of polysilicon. The first layer of polysilicon is patterned twice, once before the second polysilicon layer is deposited, and again as part of the etch of the second layer of polysilicon. Stringers of the second layer of polysilicon can form along the edge of the first etch of the first layer of polysilicon. The first etch of the first layer of polysilicon is patterned so that even if these stringers are subsequently formed, there is no harm.

REFERENCES:
patent: 4475118 (1984-10-01), Klein et al.
patent: 4531203 (1985-07-01), Masuoka et al.
patent: 4561004 (1985-12-01), Ruo et al.
patent: 4663645 (1987-05-01), Komori et al.
patent: 4679171 (1987-07-01), Logwood et al.
patent: 4709351 (1987-11-01), Kajigaya

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