Polysilicon microelectric reflectors

Details Polysilicon microelectric reflectors Polysilicon microelectric reflectors

2000-11-01

2002-09-17

Sikder, Mohammad (Department: 2813)

Optical: systems and elements

Mirror

With support

C359S871000, C359S223100, C359S224200

Reexamination Certificate

active

06450654

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to microelectromechanical systems (MEMS) devices and methods of fabricating same, and more particularly to MEMS reflectors and beams and methods of fabricating same.
BACKGROUND OF THE INVENTION
Optical communication systems are increasingly being used to communicate data, voice, multimedia and/or other communications. Optical communication systems may employ optical fibers and/or free space optical communication paths. It will be understood by those having skill in the art that optical communication systems may use optical radiation in the visible, ultraviolet, infrared and/or other portions of the electromagnetic radiation spectrum.
Reflectors, such as mirrors, are widely used in optical communications systems. For example, optical cross-connect (OXC) switches can include an array of reflectors to reflect optical energy from any switch input to any switch output. Similarly, add-drop optical switches also may use an array of reflectors such as mirrors to couple various optical paths.
It has been proposed to fabricate reflectors using microelectromechanical system (MEMS) technology. As is well known to those having skill in the art, MEMS devices are potentially low cost devices, due to the use of microelectronic fabrication techniques. New functionality also may be provided, because MEMS devices can be much smaller than conventional electromechanical devices.
One well-known and widely used process for fabricating MEMS devices is the MUMPs™ process that is marketed by Cronos Integrated Microsystems, and is described in the
MUMPS™ Design Handbook,
Revision 4.0, by the present inventor Koester et al., May 1999, the disclosure of which is hereby incorporated herein by reference in its entirety. In particular, as described in the
MUMPs™ Design Handbook,
Section 1.2, the MUMPs process is a three-layer polysilicon surface micromachining process derived from work performed at the Berkeley Sensors and Actuators Center (BSAC) at the University of California in the late 1980s and early 1990s. Several modifications and enhancements have been made to increase the flexibility and versatility of the process for the multi-user environment.
The process begins with 100 mm n-type (
100
) silicon wafers of 1-2 &OHgr;-cm resistivity. The surface of the wafers are first heavily doped with phosphorus in a standard diffusion furnace using POCl
3
as the dopant source. This helps to reduce or prevent charge feedthrough to the substrate from electrostatic devices on the surface. Next, a 600 nm low-stress Low Pressure Chemical Vapor Deposition (LPCVD) silicon nitride layer is deposited on the wafers as an electrical isolation layer. This is followed directly by the deposition of a 500 nm LPCVD polysilicon film-Poly
0
. Poly
0
is then patterned by photolithography, a process that includes the coating of the wafers with photoresist, exposure of the photoresist with the appropriate mask and developing the exposed photoresist to create the desired etch mask for subsequent pattern transfer into the underlying layer. After patterning the photoresist, the Poly
0
layer is then etched in a Reactive Ion Etch (RIE) system. A 2.0 &mgr;m phosphosilicate glass (PSG) sacrificial layer is then deposited by LPCVD and annealed at 1050° C. for one hour in argon. This layer of PSG, known as a first oxide, is removed at the end of the process to free the first mechanical layer of polysilicon. The sacrificial layer is lithographically patterned with a dimpled mask and the dimples are transferred into the sacrificial PSG layer by RIE. The nominal depth of the dimples is 750 nm. The wafers are then patterned with the third mask layer, ANCHOR
1
, and reactive ion etched. This step provides anchor holes that will be filed by the Poly
1
layer.
After etching ANCHOR
1
, the first structural layer of polysilicon (Poly
1
) is deposited at a thickness of 2.0 &mgr;m. A thin (200 nm) layer of PSG is deposited over the polysilicon and the wafer is annealed at 1050° C. for one hour. The anneal dopes the polysilicon with phosphorus from the PSG layers both above and below it. The anneal also serves to significantly reduce the net stress in the Poly
1
layer. The polysilicon (and its PSG masking layer) is lithographically patterned using a mask designed to form the first structural layer POLY
1
. The PSG layer is etched to produce a hard mask for the subsequent polysilicon etch. The hard mask is more resistant to the polysilicon etch chemistry than the photoresist and ensures better transfer of the pattern into the polysilicon. After etching the polysilicon, the photoresist is stripped and the remaining oxide hard mask is removed by RIE.
After Poly
1
is etched, a second PSG layer (Second Oxide) is deposited and annealed. The Second Oxide is patterned using two different etch masks with different objectives. The POLY
1
—POLY
2
—VIA level provides for etch holes in the Second Oxide down to the Poly
1
layer. This provides a mechanical and electrical connection between the Poly
1
and Poly
2
layers. The POLY
1
—POLY
2
—VIA layer is lithographically patterned and etched by RIE. The ANCHOR
2
level is provided to etch both the First and Second Oxide layers in one step, thereby eliminating any misalignment between separately etched holes. More importantly, the ANCHOR
2
etch eliminates the need to make a cut in First Oxide unrelated to anchoring a Poly
1
structure, which needlessly exposes the substrate to subsequent processing that can damage either Poly
0
or Nitride. The ANCHOR
2
layer is lithographically patterned and etched by RIE in the same way as POLY
1
—POLY
2
—VIA.
The second structural layer, Poly
2
, is then deposited (1.5 &mgr;m thick) followed by the deposition of 200 nm PSG. As with Poly
1
, the thin PSG layer acts as both an etch mask and dopant source for Poly
2
. The wafer is annealed for one hour at 1050° C. to dope the polysilicon and reduce the residual film stress. The Poly
2
layer is lithographically patterned with the seventh mask (POLY
2
) and the PSG and polysilicon layers are etched by RIE using the same processing conditions as for Poly
1
. The photoresist then is stripped and the masking oxide is removed. The final deposited layer in the MUMPs process is a 0.5 &mgr;m metal layer including about 200 Å of a chromium adhesion layer and about 5000 Å of gold, that provides for probing, bonding, electrical routing and highly reflective mirror surfaces. The wafer is patterned lithographically with the eighth mask (METAL) and the metal is deposited and patterned using lift-off. The wafers are diced, sorted and shipped to the MUMPs user for sacrificial release and test. The release is performed by immersing the chip in a bath of 49% HF (room temperature) for 1.5-2 minutes. This is followed by several minutes in DI water and then alcohol to reduce stiction followed by at least 10 minutes in an oven at 1000° C.
Microelectronic reflectors have been fabricated with the above-described MUMPs process, using a multilayer polysilicon base, a chromium adhesion layer and a gold reflective surface. Unfortunately, it may be difficult to form planar microelectronic reflectors using the above-described MUMPs process. In particular, stress gradients in the stacked polysilicon layers in conjunction with the internal stress of the deposited metal or metals, may produce reflectors that are not acceptably flat.
More particularly, it is known that phosphorus-doped polysilicon films may be slightly compressive. See, for example, the publication by Lee et al. entitled
Effects of Phosphorus on Stress of Multi-Stacked Polysilicon Film and Single Crystalline Silicon,
Journal of Micromechanical Micoengineering, Volume 9, pp. 252-263, Feb. 1999. Moreover, it is also known that the intrinsic film stress of most evaporated metal films is tensile. However, it may be difficult to fabricate a gold layer that has intrinsic film stress that is equal and opposite to the stress in the polysilicon layer or layers.
Finally, gold also has a high self-diffusion rate, and has bee

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