Polysilicon etch useful during the manufacture of a...

Details Polysilicon etch useful during the manufacture of a... Polysilicon etch useful during the manufacture of a...

1999-12-10

2004-04-20

Goudreau, George A. (Department: 1763)

Cleaning and liquid contact with solids

Processes

Including application of electrical radiant or wave energy...

C438S725000, C438S719000, C438S714000, C438S734000

Reexamination Certificate

active

06722376

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to the field of semiconductor assembly, and more specifically to a polysilicon etch which is particularly useful for removing polysilicon stringers.
BACKGROUND OF THE INVENTION
During the manufacture of semiconductor devices such as dynamic random access memories (DRAMs), static random access memories (SRAMs), microprocessors, logic, etc., several structures are commonly formed. With reference to
FIG. 1
, a semiconductor wafer substrate assembly
10
is provided. The wafer assembly typically comprises a semiconductor wafer
12
having a transistor stack
14
formed thereon. With current technology, for example a 64 megabit DRAM manufactured with 0.18-micron line widths, each wafer stack comprises gate oxide
16
about 60 angstroms (Å) thick, a polysilicon control gate (word line)
18
about 800 Å thick, a silicide layer
20
about 1,000 Å thick, a nitride cap
22
about 2,000 Å thick, and a pair of oxide spacers
24
. The spacing between each stack (between adjacent spacers) is about 1,300 Å. Such a structure is easily manufactured by one of ordinary skill in the art.
FIG. 1
further depicts a doped blanket polysilicon layer
26
, for example about 3,500 Å thick which is provided to form a landing pad for a contact. A patterned photoresist mask
28
is formed over the polysilicon layer
26
and an anisotropic polysilicon etch is performed to define the landing pad. To etch the polysilicon layer depicted, a conventional etch comprises 90 standard cubic centimeters (sccm) Cl
2
and 10 sccm NF
3
at a pressure of 300 millitorr (mTorr) and 100 watts power to clear the majority of the exposed polysilicon, then the pressure is increased and SF
6
is added toward the end of the etch in an attempt to clear any residual material from the exposed regions.
A desired resulting structure is depicted in
FIG. 2
which depicts a clean removal of the exposed polysilicon and no undercutting of the resist. However, with severe topology having narrow spaces between the relatively high transistor gate stacks, a more common result is depicted in FIG.
3
. Stringers
30
can form in the recesses as it is difficult to clear all the polysilicon from narrow, deep spaces found with high-density semiconductor devices, even with the increase in pressure and addition of SF
6
in the conventional etch described above. Stringers, which form especially in corners, are well known in the art to cause shorting and result in malfunctioning semiconductor devices.
Another method used in an attempt to reduce stringers includes performing a series of alternating anisotropic and isotropic etches, with the anisotropic etches removing the polysilicon in a substantially vertical direction and the isotropic etches removing the polysilicon in both horizontal and vertical directions. One problem with this method is that the isotropic etches undercut the photoresist
28
and narrow the width of the polysilicon feature
26
. Thus the critical dimension (CD) of the polysilicon feature is wider than would be required if the photoresist was not undercut, and thus the alignment tolerance is reduced. For example, with a device using 0.18 micron line widths a typical undercut is about 0.03 microns on each side (0.06 microns total). Thus the feature must be patterned for a 30% undercut tolerance. The additional space required for this allowance is a concern especially as the number of features on the device increases.
As device generations progress, the spaces between transistor stacks will decrease thereby exacerbating the problem of remaining stringers. A method which removes polysilicon, and particularly which removes stringers from severe topology, would be desirable.
SUMMARY OF THE INVENTION
The present invention provides a new method which reduces problems associated with the manufacture of semiconductor devices, particularly problems associated with etching polysilicon in narrow, deep openings associated with severe topology. In accordance with one embodiment of the invention, a semiconductor wafer substrate assembly is provided having adjacent structures which form an opening such as a trench or recess. A layer of polysilicon is formed over the wafer substrate assembly and within the opening, and a patterned photoresist layer is formed over the blanket polysilicon. An etch is performed using one of several embodiments of an inventive etch described in detail below. The inventive etch improves removal of the polysilicon from the opening and reduces the likelihood of stringers remaining after the etch.
Objects and advantages will become apparent to those skilled in the art from the following detailed description read in conjunction with the appended claims and the drawings attached hereto.


REFERENCES:
patent: 4818334 (1989-04-01), Shwartzman et al.
patent: 5030590 (1991-07-01), Amini et al.
patent: 5147499 (1992-09-01), Szwejkowski et al.
patent: 5228950 (1993-07-01), Webb et al.
patent: 5792708 (1998-08-01), Zhou
patent: 5976769 (1999-11-01), Chapman
patent: 6001688 (1999-12-01), Rizzuto

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