Polysilicon emitter and a polysilicon gate using the same etch o

Details Polysilicon emitter and a polysilicon gate using the same etch o Polysilicon emitter and a polysilicon gate using the same etch o

1991-05-02

1992-06-23

Mintel, William

357 41, 357 40, 357 59, 357 34, 357 35, H01L 2702, H01L 2904, H01L 2972

Patent

active

051248174

ABSTRACT:
Bipolar and MOS devices are made simultaneously using a single fabrication process. In one embodiment of the invention, a silicon substrate is divided into bipolar and MOS regions. A thin layer of gate oxide, having a thickness in the range of from approximately 150 angstroms to 300 angstroms, is thermally grown on the silicon substrate. A thin layer of polycrystalline silicon, having a thickness in the range of from approximately 500 angstroms to 1000 angstroms is deposited on the gate oxide layer to protect the gate oxide layer during subsequent processing. Both the thin polysilicon layer and the gate oxide layer are removed from the bipolar region where the emitter is to be formed. To maintain the integrity of the gate oxide layer during etching, a photoresist mask used during the polysilicon etch is retained during the gate oxide etch, and the gate oxide is etched in a buffered oxide solution. A thick layer of polysilicon then is deposited on the bipolar and MOS regions of the silicon substrate, and the substrate is masked and etched for forming the emitter and gates of the bipolar and MOS devices, respectively.

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