Polysilicon-doped-first CMOS process

Details Polysilicon-doped-first CMOS process Polysilicon-doped-first CMOS process

1981-12-18

1983-12-27

Roy, Upendra

Metal treatment

Compositions

Heat treating

29571, 29576B, 29578, 148187, 357 42, 357 91, H01L 2122, H01L 2978, H01L 1114

Patent

active

044228856

ABSTRACT:
Disclosed is a process for forming self-aligned polysilicon gates and interconnecting conductors having a single conductivity and single impurity type in CMOS integrated circuits. After forming a polysilicon layer over the gate oxide, the polysilicon is doped with n-type impurities. Next, the polysilicon is covered with a relatively thick oxide serving as an implantation mask and then patterned into gates and conductors. Finally, by using ion implantation sources and drains for the p-FET and n-FET are formed in a self-aligned relationship with the corresponding gates.

REFERENCES:
patent: 4224733 (1980-09-01), Spadea
patent: 4277291 (1981-07-01), Cerofolini et al.
patent: 4280272 (1981-07-01), Egawa et al.
patent: 4295897 (1981-10-01), Tubbs et al.
patent: 4306916 (1981-12-01), Wollesen et al.
patent: 4314857 (1982-02-01), Aitken
patent: 4345366 (1982-08-01), Brower

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