Oscillators – Automatic frequency stabilization using a phase or frequency... – Plural a.f.s. for a single oscillator
Reexamination Certificate
2001-04-03
2003-01-21
Pascal, Robert (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Plural a.f.s. for a single oscillator
C331S010000, C327S115000
Reexamination Certificate
active
06509800
ABSTRACT:
TECHNICAL FIELD
The invention relates to microwave synthesizers. In particular, the invention relates to the synthesis of signals using a fractional-N phase locked loop synthesizer.
BACKGROUND ART
A frequency synthesizer is a signal source device that generates an output signal from one or more reference signals. In general, frequency synthesizers produce a signal consisting of a single frequency selected from among several discrete frequencies available by virtue of the design of the synthesizer. Frequency synthesizers of various forms and designs have been found to be highly useful if not essential in a wide variety of applications including FM radios, radar systems, cellular and PCS telephone systems, and test equipment such as spectrum analyzers and signal generators.
In particular, frequency synthesizers have proven to be essential in modern communications systems. The technical advancements in modern communications and measurement systems are producing an ever-increasing demand for higher levels of performance from the frequency synthesizers used in these systems. The higher levels of performance that are required in modern frequency synthesizers run the full range of typical synthesizer performance specifications, including improved phase noise, better spectral purity, faster frequency switching or tuning speed, and smaller frequency tuning step size specifications. Concomitant with increased performance requirements are market forces surrounding modern communications and measurement systems that are placing demands for lower cost on modern frequency synthesizers.
In general, a frequency synthesizer produces or synthesizes an output signal having a selectable or “tunable” frequency. Although not always, the signal produced is typically at a higher frequency than that of the reference signal(s). The signal generated by a frequency synthesizer is typically a very stable, spectrally pure, single frequency signal having low or sometimes even very low phase noise. However, unlike other signal sources such as voltage controlled oscillators (VCO), a given frequency synthesizer generally is capable of producing only a finite, albeit often large, number of selectable, discrete frequencies as an output signal. The frequency spacing between adjacent selectable frequencies in the output signal is referred to as the “step size” or “frequency resolution” of the synthesizer. Frequency synthesizers are most often used where stepped tuning is acceptable and where the frequency stability/precision and spectral purity are of paramount importance.
A number of different types of frequency synthesizers or methods of frequency synthesis are known in the art including direct frequency harmonic generation, direct digital synthesis (DDS), and phase locked loop (PLL) frequency synthesis. The direct frequency harmonic generation synthesizer utilizes a non-linear device, such as a step recovery diode or comb generator, to produce a large number frequency harmonics of a reference signal source frequency. These harmonics are then used directly or combined with each other to produce a desired output frequency value. The DDS uses a digital to analog converter (DAC) to convert a digital data stream into an analog output signal. The digital data stream is a digital representation of a sampled version of the desired output signal, thus the DDS directly synthesizes the output signal. In a PLL synthesizer, a negative feedback loop is used to compare and “phase lock” the output signal of a tunable frequency source, such as a VCO, to a stable reference signal. When locked, the PLL output frequency is typically a multiple of the reference signal or linear combination of the reference signal and other signals generated by the synthesizer. In addition, there are also hybrid synthesizers that combine one or more of these or other various frequency synthesis approaches.
As is the case with frequency synthesizers in general, there are also many ways to realize a PLL synthesizer. In some applications, a simple single loop approach is acceptable or even preferred. In other instances, more complicated, multiple loop approaches are used. Moreover, it is often advantageous to incorporate harmonic generators and/or a DDS into a PLL, thereby improving the synthesizer performance and/or decreasing the cost. Strictly speaking, while synthesizers with DDS and harmonic generators are properly classed as hybrid synthesizers, common practice is to refer to these as PLL synthesizers, since the PLL is the principle means of synthesizing the output signal.
FIG. 1
illustrates a block diagram of a basic, single loop PLL synthesizer (SLS) used to synthesize a signal from a stable reference signal. The basic SLS comprises a voltage-controlled oscillator (VCO)
10
, a loop frequency divider
16
, a reference oscillator
18
, a phase/frequency comparator or detector (PFD)
20
, and a loop integrator or loop filter/amplifier
22
. Often a reference frequency divider
24
is included between the reference oscillator
18
and the PFD
20
. The VCO
10
produces an output signal, the frequency of which is proportional to an input control voltage. The output signal produced by the VCO
10
is divided by the frequency divider
16
to create a lower frequency signal. The frequency dividers
16
,
24
are apparatuses that accept a signal at a frequency f and produce an output signal at a frequency f/N f/M, where N and M are integer division factors, of the frequency dividers
16
,
24
, respectively.
The signal produced by the frequency divider
16
is compared by the PFD
20
to a divided reference frequency signal produced by the reference frequency divider
24
acting on a reference signal from the reference oscillator
18
. The PFD
20
, in turn, produces an error voltage signal that is proportional to the phase/frequency difference between the frequency of the output signal of the frequency divider
16
and the divided reference signal frequency fref/M, where M is the division factor of the reference frequency divider
24
. The error voltage is integrated by the loop integrator
22
to produce the input control voltage that is applied to the VCO
10
.
In some implementations, an output amplifier
12
and a loop amplifier
14
are included in the basic SLS. The output amplifier
12
is used to amplify the output signal produced by the SLS. The loop amplifier
14
is used to amplify the portion of the output signal that is used by the frequency divider
16
. The loop amplifier
14
also provides a reverse isolation between the frequency divider
16
and the SLS output.
The action of the negative feedback loop of the PLL eventually causes or forces the error voltage to equal zero. In essence, the VCO
10
output signal is automatically adjusted by the feedback loop until the frequency of the divided signal produced by the frequency divider
16
equals the frequency of the reference signal. When the error voltage has been made equal to zero by the action of the feedback loop, the loop is said to be “locked” to the reference source. When locked, the loop maintains the relationship of equation (1).
f=fref*
(
N/M
) (1)
The frequency f of the output signal can be changed by changing either the integer division factor N of the loop divider
16
or the reference signal frequency and/or the integer division factor M of the reference divider
24
. Generally but not always, the reference signal frequency and reference divider division factor M are fixed and the loop division factor N is changed to affect tuning in a single loop frequency synthesizer (SLS). In other words, tuning of the synthesizer is accomplished by changing the value of N or an equivalent control instruction that is applied to a control input on the loop divider
16
.
The basic SLS has a major performance limitation in that the phase noise produced by the SLS is essentially proportional to the phase noise of the reference source multiplied by the combined division factor N/M. The higher the loop division factor N the more phase noise is produced by the SLS. This im
Agilent Technologie,s Inc.
Chang Joseph
Pascal Robert
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