Polyphase filter and receiver using the same

Details Polyphase filter and receiver using the same Polyphase filter and receiver using the same

2000-09-05

2003-03-04

Pascal, Robert (Department: 2817)

Wave transmission lines and networks

Coupling networks

Frequency domain filters utilizing only lumped parameters

C333S168000

Reexamination Certificate

active

06529100

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a polyphase filter and a receiver using thereof.
2. Description of the Related Art
With regard to digital audio broadcasting system, DAB (Digital Audio Broadcasting complies with Eureka 147 standard) system is adopted in Europe, and ISDB-T (Integrated Services Digital Broadcasting for Terrestrial) system is proposed in Japan.
ISDB-T system employs:
transmission band width of 432 kHz (for narrow-band ISDB-T system);
modulation system of OFDM (Orthogonal Frequency Division Multiplex); and
multiplexing system of MPEG2 (Moving Picture Experts Group 2); which enable simultaneous broadcasting of digital audio data and digital data in a plurality of channels. Broadcasting based on the narrow-band ISDB-T system is now planned to use the current VHF television broadcasting band.
One example of an ISDB-T receiver is typically composed as shown in FIG.
5
. The figure shows a narrow-band ISDB-T receiver employing a super heterodyne configuration.
Broadcasting wave based on the narrow-band ISDB-T system is received by an antenna
11
, the received signal is then fed to an antenna tuning circuit
12
based on the electronic tuning system, thereby a received signal S
RX
having a target frequency is extracted. The extracted signal S
RX
is then fed to mixer circuits
15
I,
15
Q via a variable gain amplifier
13
and an inter-stage tuning circuit
14
based on the electronic tuning system.
On the other hand, an oscillation signal having a predetermined frequency is generated by a PLL (Phase Locked Loop)
31
, the oscillation signal from the PLL
31
is then fed to a frequency dividing circuit
32
, where the oscillation signal is divided into two signals having a frequency higher, for example, by 500 kHz than a carrier frequency (center frequency) of the received signal S
RX
and differ by 90° with each other in phase, the divided signals are then supplied to the mixer circuits
15
I,
15
Q as local oscillation signals.
Thus the received signal S
RX
is frequency-converted at the mixer circuits
15
I,
15
Q to generate two intermediate frequency signals S
IFI
and S
IFQ
(having a center frequency of 500 kHz) differ by 90° with each other in phase, that is, an in-phase intermediate frequency signal S
IFI
and a quadrature intermediate frequency signal S
IFQ
orthogonal with each other.
In this process, a part of control voltage supplied from the PLL
31
to a variable capacity diode (not shown) of its VCO (Voltage Controlled Oscillator), is extracted, and the extracted control voltage is fed to the tuning circuit
12
as a tuning voltage, which allows tuning to the received signal S
RX
.
The intermediate frequency signals S
IFI
and S
IFQ
from the mixer circuits
15
I,
15
Q are then individually supplied to phase shifting circuits
17
I,
17
Q via the low pass filters
16
I,
16
Q, where the signals S
IFI
and S
IFQ
are phase-shifted by &phgr; and &phgr;+90°, respectively. The phase-shifted signals are then supplied to an adder circuit
18
, from which an intermediate frequency signal S
IF
having only a desired signal component is extracted while image signal components being canceled.
The intermediate frequency signal S
IF
is then supplied on a signal line comprising a bandpass filter
19
for filtering intermediate frequency component, a variable gain amplifier
21
for AGC (Automatic Gain Control) and a low pass filter
22
to a demodulation circuit
23
, where the signal is subjected to demodulation processing corresponded to the modulation processing at the time of the ISDB-T transmission, and audio signals L, R of a desired program selected from a plurality of programs (channels) are extracted from such demodulation circuit
23
.
Such receiver can be integrated into an one-chip integrated circuit (IC) except the tuning circuits
12
,
14
, an oscillation circuit of VCO in the PLL
31
and the demodulation circuit
23
.
The phase shifting circuits
17
I,
17
Q and the adder circuit
18
now can be composed by a polyphase filter
17
as shown in FIG.
6
.
In this configuration, a serial connection circuit consisting of a resistor R
11
and a capacitor C
11
is inserted between input terminals
17
A and
17
B; a serial connection circuit consisting of a resistor R
21
and a capacitor C
21
is inserted between input terminals
17
B and
17
C; a serial connection circuit consisting of a resistor R
31
and a capacitor C
31
is inserted between input terminals
17
C and
17
D; and a serial connection circuit consisting of a resistor R
41
and a capacitor C
41
is inserted between input terminals
17
D and
17
A.
A serial circuit consisting of a resistor R
12
and a capacitor C
12
is inserted between the output side of the resistor R
11
(connection point of the resistor R
11
and the capacitor C
11
) and the output side of the resistor R
21
(connection point of the resistor R
21
and the capacitor C
21
); a serial circuit consisting of a resistor R
22
and a capacitor C
22
is inserted between the output sides of the resistor R
21
and the output side of the resistor R
31
; a serial circuit consisting of a resistor R
32
and a capacitor C
32
is inserted between the output side of the resistor R
31
and the output side of the resistor R
41
; and a serial circuit consisting of a resistor R
42
and a capacitor C
42
is inserted between the output side of the resistor R
41
and the output side of the resistor R
11
.
Similarly, serial connection circuits individually consisting of resistors R
13
to R
43
and capacitors C
13
to C
43
are connected to the respective output sides of the resistors R
12
to R
42
. The individual output sides of the resistors R
13
and R
23
are connected to an output terminal
17
E, and the individual output sides of the resistors R
33
and R
43
are connected to an output terminal
17
F.
The outputs from the low pass filters
16
I and
16
Q are balanced type, and the intermediate frequency signal S
IFI
output from the low pass filter
16
I is supplied between the output terminals
17
A and
17
C, and the intermediate frequency signal S
IFQ
output from the low pass filter
16
Q is supplied between the output terminals
17
B and
17
D. Thus an intermediate frequency signal having only a desired signal component is output in a balanced type between the output terminals
17
E and
17
F while image signal components being canceled.
Such polyphase filter
17
is advantageous in that it can be fabricated into an IC, and in that it is stable in the characteristic against non-uniformity in the fabrication of the IC devices and can ensure thorough elimination of the image signal component according to the foregoing method, since the resistors R
11
to R
43
and the capacitors C
11
to C
43
composing the polyphase filter
17
are in bridge connection.
In the polyphase filter
17
, a frequency f
17
receiving 90° phase shifting is now expressed as
f
17
=1/(2
&pgr;CR
)
where, CR is a product of values for the resistors and the capacitors in the individual stages. The number of the stages of the polyphase filter
17
is determined based on the amount of attenuation required for suppressing the image signal components and specific band.
When fabricating the polyphase filter
17
into an IC, the capacitors C
11
to C
43
can be constituted by a metal-insulator-semiconductor (MIS) capacitor as shown in FIG.
7
A. In this figure, on a p-type semiconductor substrate
71
, formed are an n-type epitaxial layer
72
, an n
+
-type buried region
73
and a p
+
-type isolation region
74
.
An n
+
-type semiconductor layer
75
is formed in a superficial area of the epitaxial layer
72
, and thereon an SiO
2
layer
76
and an extra thin insulating layer
77
are formed. Further thereon an electrode
78
is formed so as to contact the semiconductor layer
75
, and an electrode
79
is formed so as to be opposed to the n
+
-type semiconductor layer
75
while being interposed by the insulating layer
77
. The electrodes
78
,
79
are generally made of aluminum.

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