Polynomial and integer multiplication

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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Reexamination Certificate

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07447726

ABSTRACT:
A method and apparatus for generating a plurality of concurrent significant bits forming at least a portion of a product from at least two partial products, the method comprising the following steps: for each of a plurality of said concurrent predetermined significant bits performing steps (i) to (iii): (i) performing an addition of bits of a predetermined significance from each of said plurality of partial products having a bit of said predetermined significance; (ii) forming an intermediate sum of said predetermined significance from the least significant bit of said additions; (iii) forming at least one intermediate carry of a higher significance from said higher significant bits of said sum; and detecting if said partial products are formed from integers or polynomials; and outputting said plurality of intermediate sum bits formed during steps (i) to (iii) as a plurality of product bits of corresponding significance in response to detection of polynomials; or combining said intermediate carrys and said intermediate sum bits with a same significance to produce a product bit of a corresponding significance in response to detection of integers, and outputting said combination as a plurality of product bits of corresponding significance.

REFERENCES:
patent: 6915322 (2005-07-01), Hong
patent: 7124162 (2006-10-01), Combes et al.
patent: 7139787 (2006-11-01), Rarick et al.
patent: 7266579 (2007-09-01), Dupaquis et al.
E. Savas et al., A Scalable and Unified Multiplier Architecture for Finite Fields FDF(p) and GF(2m) , Electrical & Computer Engineering , Oregon State University, pp. 1-20, Aug. 2000.
Lai-Sze Au et al., Unitied Radix-4 Multiplier for GF(p) and GF(2Λn), Cardiff School of Engineering, United Kingdom Jun. 2003.

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