Polymeric dielectric layers having low dielectric constants...

Details Polymeric dielectric layers having low dielectric constants... Polymeric dielectric layers having low dielectric constants...

2000-07-10

2002-09-24

Everhart, Caridad (Department: 2825)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S759000, C438S780000

Reexamination Certificate

active

06455934

ABSTRACT:

BACKGROUND OF THE INVENTION
As device density continues to increase in integrated circuits, line widths and line separation distances must become smaller. As a result, detrimental capacitive effects may be experienced in metal lines connecting transistors on a substrate. The capacitive effects can result in two ways. First, two adjacent metal lines on a single metalization layer may be sufficiently close that they, together with the dielectric separating them, act as a capacitor. Second, metal lines on two adjacent metalization layers that are lined substantially on a common vertical axis can, together with the dielectric separating them, act as a capacitor. In either case, when a change in potential is applied to a line with the goal of conducting current across that line, the applied change in voltage is resisted by the presence of adjacent metal lines which act as plates of a capacitor. Further, signals on adjacent lines may interfere with one another resulting in “crosstalk.”
These phenomena can be understood with reference to FIG.
1
. As shown, a typical integrated circuit cross-section
8
includes a semiconductor substrate
10
on which polysilicon gates
12
and field oxide
14
are formed. An interlayer dielectric
16
(or “ILD”) entirely covers the field oxide, the gate electrodes, and the substrate. Commonly, the interlayer dielectric
16
is made from a phosphosilicate glass. A first metalization layer
18
is provided on top of ILD
16
and patterned to form metal lines as shown. Note that vias (openings) are formed through ILD
16
and include metal contacts
27
connecting polysilicon gate electrodes
12
to the metal lines of metalization layer
18
.
After layer
18
has been patterned, an intermetal dielectric
20
(or “IMD”) is formed on top of metalization lines
18
and insulates those lines from a second metalization layer
22
which is also patterned to form separate metal lines. Interconnects
28
through IMD
20
connect the lines of first metalization layer
18
to the lines of second metalization layer
22
. To insulate the conductive lines of the second metalization layer, a second intermetal dielectric layer
26
is formed on top of second metalization layer
22
.
As shown with reference to first metalization layer
18
and second metalization layer
22
, the individual metal lines of that metal layer may be disposed relatively close to one another. In one typical process, the height of the metal lines is about 0.7 micrometers and the width of such metal lines is about 0.4 micrometers. In addition, the individual lines may be separated by as little as 0.4 micrometers. When this is the case, the capacitive coupling between adjacent lines becomes quite pronounced.
In a technology having the line dimensions and separations indicated above, transistor switching speed may become limited by the metal lines. In this example, transistors connected by lines of greater than about 300 micrometers in length will begin to have their switching speed limited by the metal lines. For shorter line lengths, the switching speed is limited by the individual transistors. For longer line lengths, the switching speed is definitely limited by the capacitive effects experienced in the lines.
In many designs at least some of the transistors are separated by lines of at least 300 micrometers in length. Therefore, the capacitive coupling between adjacent lines represents a source of performance degradation. With this in mind, IC designers have investigated various approaches to reducing the capacitive coupling between adjacent lines and metalization layers. Of particular interest are those efforts which have strived to reduce the dielectric constant of the insulator material provided between adjacent metalization layers. A material's dielectric constant is a measure of its ability to store electrical energy. The lower its dielectric constant, the less the material can behave as if it were a capacitor. And the less charge that it stores, the less any signals passing along adjacent conductive lines will be garbled or delayed by electrical interference.
One approach to reducing dielectric constant has involved the introduction of fluorine or fluoride species into silicon dioxide IMDs. This approach has been found largely unsatisfactory because free fluorine radicals and/or ions generated during the IMD deposition process can be particularly chemically aggressive and therefore hard to control. Other approaches to reducing the dielectric constant have involved replacing the silicon dioxide conventionally employed in IMDs with an organic polymeric material. These materials may have dielectric constants as low as about 2.0; silicon dioxide based materials in conventional IMDs have dielectric constants of about 3.9. Unfortunately, it can be quite difficult to find polymeric materials which have a thermal stability adequate to withstand high temperature deposition and annealing process steps.
Commonly, during metal deposition steps, the wafer under process is exposed to temperatures of over 350° centigrade. Thus, alternative IMD materials must be able to withstand temperatures in the neighborhood of at least 350-450° centigrade. Unfortunately, suitable polymers rarely can withstand such temperatures. If the polymers are cross-linked, they typically decompose at temperatures above 350° centigrade. A material that loses more than 0.1% of its mass on exposure to a 450° centigrade environment for 1 hour is unsuitable as an IMD dielectric. The lost polymer forms volatile materials which interfere with other process steps and create unacceptably high concentrations of dangling bonds. Thermoplastic polymers (which are not cross-linked) may also decompose at high temperatures. In addition, they may liquefy and simply flow off of the wafer. Obviously, such materials are unsuitable for use in integrated circuit fabrication.
Despite these problems, ongoing research efforts have identified certain thermally stable polymers which show substantial promise as low dielectric constant IMD materials. Often, such materials are at least slightly cross-linked and/or have a fairly rigid polymer backbone. For example, these materials may include ring structures such as phenyl groups or cyclic imide groups. Of particular note, many of the most promising polymeric IMD materials are fluorinated polymers. Thus, some promising materials include polycyclic backbones having substantial fluorine substitution. One material receiving much attention is polyfluoropyreline. This material is sufficiently stable at 450° centigrade that it may be employed in conventional integrated circuit fabrication processes.
Unfortunately, it has been observed that polyfluoropyreline and related thermally stable fluorinated polymers do not adhere well to adjacent metalization lines. This is not surprising as fluorinated polymers are widely known to have very poor adhesive properties due to their low surface energies. Obviously, until these adhesion problems are overcome, thermally stable fluorinated polymers will not realize their potential as commercially viable IMD materials.
SUMMARY OF THE INVENTION
The present invention provides thermally stable polymeric IMDs and ILDs having enhanced adhesiveness by introduction of an adhesive material in the IMD or ILD polymeric material. In the preferred embodiments, the adhesive material resides only at the interface of the IMD or ILD with adjacent metalization or polysilicon layers.
One aspect of the invention generally provides an electronic circuit having a dielectric material for electrically isolating one or more conductive pathways. Specifically, the dielectric material includes a thermally stable polymeric material having its adhesiveness to the one or more conductive pathways improved by a polar material disposed on at least an interface between the polymeric material and the one or more conductive pathways. When the electronic circuit is an integrated circuit, at least three options for using the invention are available: (a) the dielectric material is an intermetal dielectric and

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