Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2000-10-02
2003-02-11
Fahm, Wael (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S125000, C257S701000, C257S737000, C257S778000
Reexamination Certificate
active
06518088
ABSTRACT:
BACKGROUND OF THE INVENTION
Integrated circuits are being given higher and higher numbers of terminals and are thereby continuing to be miniaturized further. The difficulties with the application of solder paste and with equipping to be anticipated given this increasing miniaturization are to be overcome by new housing forms, whereby single, few or multi chip modules in a ball grid array package are to be particularly emphasized (German periodical productomic 5, 1994, pages 54, 55). These modules are based on a through-conducted substrate on which the chips are contacted, for example, via contacting wires or with flip-chip mounting. The ball grid array (BGA), which is often also referred to as solder grid array, land grid array or solder bump array, is situated at the underside of the substrate. At the underside of the substrate, the ball grid array comprises planarly arranged solder bumps that enable a surface mounting on the printed circuit boards or assemblies. High numbers of terminals in a rough grid of, for example, 1.27 mm can be realized as a result of the planar arrangement of the solder bumps.
Injection molded parts with integrated interconnections are employed instead of conventional printed circuits in what is referred to as MID technology (MID=Molded Interconnection Devices). High-grade thermoplastics that are suitable for the injection molding of three-dimensional substrates are the basis of this technology. Such thermoplastics are distinguished over traditional substrate materials for printed circuits by better mechanical, thermal, chemical, electrical and environmental properties. In a specific direction of MID technology, what is referred to as SIL technology (SIL=Spritzgiessteile mit integrierten Leiterzugen [injection molded parts with integrated interconnections]), the structuring of a metal layer applied onto the injection molded parts ensues with a specific laser structuring method, foregoing the otherwise standard mask technique. A number of mechanical and electrical functions can thereby be integrated into the three-dimensional injection molded parts with structured metallization. The housing carrier function simultaneously assumes guides and snap-in connections, whereas the metallization layer, in addition to the wiring and connecting function, also serves as electromagnetic shielding and sees to a good heat elimination. Further details about the manufacture of three-dimensional injection molded parts with integrated connector trains derive, for example, from German patent DE-A-37 32 249 or European patent EP-A-0 361 192.
U.S. Pat. No. 5,081,520 discloses a method for fastening IC chips on substrates wherein the substrates are produced as injection molded parts with integrated bumps for the fastening of the IC chips. A connecting layer is applied after the metallization, so that the IC chips can be secured to the substrates, whereby the chip terminal surfaces are electrically conductively connected to the allocated metallizations of the bumps.
SUMMARY OF THE INVENTION
The invention is based on the problem of creating a new structural shape for single, few or multi chip modules that exhibits the advantages of MID technology and enables a planar arrangement of the outside terminals as in a ball grid array.
To this end, a polymer stud grid array is provided. The polymer stud grid array has an injection molded, three-dimensional substrate composed of an electrically insulating polymer. Polymer studs are co-formed on the underside of the substrate during injection molding. Outside terminals are formed on the polymer studs by a solderable end surface. Interconnections are fashioned at least on the underside of the substrate that connect the outside terminals to inside terminals. At least one chip is arranged on the substrate whose terminals are electrically conductively connected to the inside terminals wherein the polymer studs form the polymer studs planarly arranged in the grid array on the underside of the substrate.
Based on the ball grid array (BGA), the inventive structural shape is referred to as polymer stud grid array (PSGA), whereby the term “polymer stud” is intended to indicate the polymer bumps that are co-shaped in the injection molding of the substrate. In addition to the simple and cost-beneficial manufacture of the polymer studs in the injection molding of the substrate, the manufacture of the outside terminals on the polymer studs can also be undertaken with minimum outlay together with the manufacture of the interconnections standard in MID technology or, respectively, SIL technology. On the basis of the fine laser structuring preferred in SIL technology, the outside terminals on the polymer studs can be realized in a very fine grid with high numbers of terminals. It must also be emphasized that the temperature expansion of the polymer studs corresponds to the temperature expansion of the substrate and of the printed circuit board accepting the module. If mechanical stresses occur, then the polymer studs enable at least a partial compensation due to their elastic properties. As a result of the shape stability of the outside terminals formed on the polymer studs, the dependability given repair and replacement can also be substantially enhanced compared to ball grid arrays with their outside terminals formed by solder bumps.
In an embodiment, the polymer stud array enables a sunken mounting of the chips in troughs of the injection molded substrates, as a result whereof an extremely low thickness of the resultant single, few or multi chip modules can be realized. The sunken mounting also enables an optimum protection of the chips as well as a simple and hermetically tight encapsulation.
In an embodiment, the polymer stud array enables a contacting of the chips in the proven wire bond technique. In another embodiment, the attachment of the contacting wires can be facilitated by the arrangement of the inside terminals on a step of the trough.
In an embodiment, the flip-chip technique can also be successfully employed for the contacting of the chips.
In an embodiment, the flip-chip contacting is provided for direct connection of the chip terminals to the allocated inside terminals wherein the chip terminals can be fashioned as meltable bumps.
In an embodiment, however, the inside terminals in the flip-chip contacting can also be formed by polymer studs co-formed in the injection molding of the substrate and provided with a solderable end surface. As a result thereof, first, normal chips without meltable bumps can be employed, whereas, second, the manufacture and metallization of the polymer studs in the MID technology can be implemented practically without additional outlay. Additionally, the polymer studs have the advantage that they allow an elastic compensation between different expansion behavior of substrate and chip.
Additional features and advantages of the present invention are described in, and will be apparent from, the detailed description of the presently preferred embodiments and from the drawings.
REFERENCES:
patent: 3483308 (1969-12-01), Wakely
patent: 4618739 (1986-10-01), Theobald
patent: 4837184 (1989-06-01), Lin et al.
patent: 5022045 (1991-06-01), Elliot
patent: 5081520 (1992-01-01), Yoshii et al.
patent: 5128746 (1992-07-01), Pennisi et al.
patent: 5172485 (1992-12-01), Gerhard et al.
patent: 5471011 (1995-11-01), Maslakow
patent: 5477087 (1995-12-01), Kawakitta et al.
patent: 5481400 (1996-01-01), Borden
patent: 5650593 (1997-07-01), McMillan et al.
patent: 5686317 (1997-11-01), Akram et al.
patent: 5824598 (1998-10-01), Yamaguchi et al.
patent: 5840622 (1998-11-01), Miles et al.
patent: 5852326 (1998-12-01), Khandros et al.
patent: 5883000 (1999-03-01), Pasch
patent: 0 480 703 (1992-04-01), None
patent: 63-220533 (1988-09-01), None
patent: 03-297152 (1991-12-01), None
Beyne Eric
Heerman Marcel
Hoof Van Rita
Puymbroeck Van Jozef
Roggen Jean
Fahm Wael
Schiff & Hardin & Waite
Siemens N.V. and Interuniversitair Micro-Electronica Centrum VZW
Toledo Fernando
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