Polyimide-insulated cube package of stacked semiconductor device

Details Polyimide-insulated cube package of stacked semiconductor device Polyimide-insulated cube package of stacked semiconductor device

1994-10-27

1995-12-26

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437211, 437214, 437217, 437219, H01L 2160

Patent

active

054787815

ABSTRACT:
A cube package of stacked silicon semiconductor chips. To accommodate cube packaging, a metal transfer layer is added over the passivated chip face to bring all of the surface electrical contacts to a common chip edge. The metal transfer layer is insulated from the chip face and from the adjacent chip in the stack by polymer layers having a low dielectric constant, and a thermal expansion coefficient matching that of the stacked chips. An adhesive polymer layer is added to strengthen the bond between the first polymer layers and the adjacent chip in the stack, by deposition of the adhesive layer and partial cure at the wafer level, and then full cure when the chips are stacked together to form the cube.

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The GEC Journal of Research, vol. 7, No. 1, 1989, GB, pp. 16-27, A. D. Trigg `design and fabrication of silicon hybrid multi-chip modules`FIG. 10.
Microelectronic Engineering, vol. 15, No. 1/4, Oct. 1991, NL, pp. 167-174, Moriya et al. `results of the three-dimensional integrated circuits project in Japan`, FIGS. 1, 2.

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