Polygraphic encryption-decryption system

Telegraphy – Systems – Printing

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178 2209, 178 2219, H04L 904

Patent

active

045202320

ABSTRACT:
A system for encoding, or encrypting, digital data wherein an invertible matrix of binary bits provides the encrypting factor or key, this invertible matrix being loaded in a memory. Blocks or sets of binary bits of data, a string of serially appearing binary bits, to be encoded are sequentially loaded into discrete, ordered stages of an input shift register, and the state of each stage is coupled as an enabling signal to sets of gates which read out the binary states of rows of the matrix configured memory. Groups of outputs from gates, conforming to columns of the matrix memory, are fed to an exclusive OR gate for each group. Then, the outputs of the exclusively OR gates for several columns of the matrix are loaded into discrete stages of an output register. The combination of the states of the output register together provide a block or polygraphic encryption, or decryption, of the binary data supplied the input register. The states of the output register are then clocked out in serial form.

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patent: 4172213 (1979-10-01), Barnes et al.
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patent: 4229818 (1980-10-01), Matyas et al.
patent: 4322577 (1982-03-01), Brandstrom
patent: 4329545 (1982-05-01), Westermayer
patent: 4343967 (1982-08-01), McArdle
patent: 4447672 (1984-05-01), Nakamura

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