Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Non-single crystal – or recrystallized – material with...
Reexamination Certificate
2006-02-21
2006-02-21
Blum, David S. (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Non-single crystal, or recrystallized, material with...
Reexamination Certificate
active
07002178
ABSTRACT:
A thin film transistor device includes a substrate, a buffer layer on the substrate, an active layer on the buffer layer, the active layer is formed of polycrystalline silicon and includes first undoped areas, a second lightly doped area, and third highly doped areas, a gate insulation layer on the buffer layer, a dual-gate electrode on the gate insulation layer including first and second gate electrodes corresponding to the first areas, an interlayer insulator on the gate insulation layer covering the dual-gate electrode, source and drain contact holes exposing the third areas, a gate contact hole penetrating the interlayer insulator to expose a portion of the dual-gate electrode, source and drain electrodes on the interlayer insulator contacting the third areas through the source and drain contact holes, and a third gate electrode on the interlayer insulator contacting the exposed portion of the dual-gate electrode through the gate contact hole.
REFERENCES:
patent: 6034748 (2000-03-01), Furuta
patent: 6249327 (2001-06-01), Murade et al.
patent: 6569717 (2003-05-01), Murade
patent: 6624051 (2003-09-01), Ohtani et al.
patent: 05-121439 (1993-05-01), None
patent: 1998-012042 (1998-11-01), None
Richard S. Muller, et al Device Electronics for Integrated Circuits second edition John Wiley and Sons, 1986, pp. 424-425.
Hoon-Ju Chung, et al. “Novel Dual-Gate Poly-Si TFT's with Intermediate Lightly Doped Region”, Asia Display/IDW '01, pp. 1737-1740.
Byung-Hyuk Min, et al. “Electrical Characteristics of New LDD Poly-Si TFT Structure Tolerant to Process Misalignment” IEEE Electron device Letters, vol. 20. No. 7, Jul. 1999.
Hoon-Ju Chung, et al. “P-5: Leakage Current Characteristics of Dual-Gate Poly-Si TFT's with Intermediate Lightly Doped Region” SID 02 Digest. pp. 217-219.
Blum David S.
LG.Philips LCD Co. , Ltd.
McKenna Long & Aldridge LLP
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