Polycrystalline semiconductor deposition in groove for device in

Details Polycrystalline semiconductor deposition in groove for device in Polycrystalline semiconductor deposition in groove for device in

1988-10-13

1989-05-23

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 67, 437 78, H01L 21265

Patent

active

048330981

ABSTRACT:
In an improved metal-oxide-semiconductor (MOS) device a polycrystalline semiconductor region is buried in a monocrystalline semiconductor substrate at the isolation region between elements of the device. A deep and narrow groove of about 1 .mu.m is formed by reactive ion etching in which the polycrystalline silicon is deposited by chemical vapor deposition. Surface polycrystalline semiconductor is removed by etching resulting in only the polycrystalline semiconductor buried in the substrate which is implanted with ions. Alternatively, polycrystalline semiconductor is deposited only in the bottom portion of the groove, ion implanted and an insulator film is formed in the remaining portion of the groove for fully isolating the polycrystalline region. Semiconductor devices prepared in accordance with the invention have flattened surfaces, reduced crystal defects and permit further miniaturization of the MOS devices.

REFERENCES:
patent: 4252579 (1981-02-01), Ho et al.
patent: 4473598 (1984-09-01), Ephrath et al.
patent: 4528047 (1985-07-01), Beyer et al.
patent: 4554728 (1985-11-01), Shepard
patent: 4569701 (1986-02-01), Oh
Doo et al., IBM Tech. Disc. Bull., vol. 8, No. 5, (Oct. 1985), pp. 802-803.
Bhatia et al., IBM Tech. Disc. Bull., vol. 25, No. 3B, (Aug. 1982), pp. 1482-1484.

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