Poly gate silicide inspection by back end etching

Details Poly gate silicide inspection by back end etching Poly gate silicide inspection by back end etching

1999-09-03

2002-11-19

Kunemund, Robert (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Liquid phase etching

C438S745000, C438S753000, C438S754000, C438S756000, C438S692000, C438S693000

Reexamination Certificate

active

06482748

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of inspecting the continuity of created poly gate silicide.
(2) Description of the Prior Art
A key aspect of the manufacturing of semiconductor devices and the performance improvements that are being made to these devices has, for many years, been device miniaturization. Smaller and denser semiconductor devices provide improved device performance together with increased functional capability of the device. This continuing increase in device miniaturization however continues to pose new problems of device design and manufacturing such as increased parasitic capacitance, increased relative impact of device contact resistance and ever increasing demands on the ability to create small and closely spaced device features. The problem of reducing contact resistance is in the art addressed by the use of silicides. For very small modern silicon devices, which are sub-micron, sub-half-micron, and even sub-quarter-micron, conventional photolithographic technique for patterning contacts will not meet the required tolerance of critical dimensions. The method of self-aligned silicide (salicide) formation, which self-registers with the contacts at the top of the polysilicon gate, the source and the drain, helps solve the problem of critical dimension tolerance. Salicides have thus become almost universal in todays high-density MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistors) devices. A metal silicide layer is for instance used on the gate electrode of the Field Effect Transistor (FET) to substantially reduce the sheet resistance of the polysilicon gate electrode. In forming a FET, the active region on the surface of the substrate in which the FET is being created is typically bounded by field oxide regions. A layer of thin oxide is formed on the substrate active device region over which layer of polysilicon is formed. The polysilicon layer is then masked and both the exposed polysilicon and the underlying thin oxide are etched to define a poly-silicon gate region separated from the substrate by thin gate oxide. A self-aligned implant of N-type dopant then forms lightly doped diffusion (LDD) source/drain regions in the substrate as a first phase in forming the substrate N+source/drain regions of the MOSFET. After the formation of oxide sidewall spacers on the sidewalls of the polysilicon gate and of the gate oxide, a second N+implant is performed to set the conductivity of the gate region to a desired level and to complete the N+ source/drain regions. Titanium is then deposited on the exposed upper surfaces of the N+ source/drain regions and the polysilicon gate region and annealed (sintered), thereby causing the titanium to react with the underlying N+ silicon of the substrate source/drain regions and the doped polysilicon gate to form titanium salicide on these surfaces. A layer of dielectric material, typically silicon oxide, is then formed. Contact openings are etched in the dielectric and a metalization layer is formed to provide contacts to the salicide on the source/drain regions and on the polysilicon gate.
The above-described MOSFET fabrication technique suffers from potential problems in the formation of source/drain regions. First, selective growth of the salicide needed for good contacts with the metalization layer requires a reaction between the titanium and underlying silicon. Therefore, the titanium must be formed on the N+ source/drain regions that must be wide enough to accommodate the photolithographic limitations in the contact opening; this results in a wider device. Also, since silicon is consumed in this process, the junction depth of the N+ source/drain regions is difficult to control and dopant depletion can occur in these regions.
Furthermore, formation of the deep, heavily doped N+ junction for the source/drain regions can result in dopant diffusion under the gate region thereby reducing the effective channel length of the MOSFET, i.e. the so-called “short channel effect”. Yet another problem that can be experienced in the above-indicated formation of the salicide regions is that it is difficult to create low sheet resistance silicide for sub-micron device features. This problem has been addressed by using not titanium but cobalt or nickel to interact with the underlying silicon and to thereby form the low resistance contact regions. Also, the polysilicon of the gate structure can be amorphized by ion implant thereby improving its sheet resistance. This latter approach can however result in crystalline damage to the silicon of the source/drain regions of the device.
The ability to achieve successful salicide formation is dependent on the integrity of the insulator spacers, on the sides of the polysilicon gate structure, during the salicide formation procedure. For example prior to metal deposition, native oxide on the exposed top surface of the polysilicon gate structure, as well as the top surface of the source and drain region, has to be removed, to allow the subsequent metal silicide formation to be successful. Native oxide will prevent the reaction between the metal and the exposed silicon surfaces during an anneal cycle. Therefore a buffered hydrofluoric acid procedure is used prior to metal deposition. However if, as a result of the buffered hydrofluoric acid metal pre-cleaning procedure, the insulator spacer (on the sides of the polysilicon gate structure) becomes defective or significantly thinned, thereby exposing polysilicon, the formation of unwanted metal silicide or bridging of the metal silicide can occur on the sides of the polysilicon gate structure. This results in gate to substrate shorting or leakage.
A number of different approaches have been advocated in the art for the formation of low resistance contact regions to the gate electrode and source/drain regions of the device, all of these approaches must be provided with a method of close inspection and monitoring of the results that are obtained while using these methods.
In the recent past, Scanning Electron Microscopes (SEM's) and Transmission Electron Microscopes (TEM's) have been used extensively for visual inspection of created layers of silicide. These methods are however time consuming whereby furthermore only localized or narrow areas of the silicide can be observed at one time. Scanning over the entire surface of the created silicide therefor requires multiple adjustments over the surface that is being observed, making this process very time consuming and labor-intensive. This process is also rather cumbersome because using an SEM requires that the specimen that is being examined must be placed into a vacuum chamber where a focused electron beam strikes the area that is being examined. The surface region of the specimen that is being examined must be electrically grounded within the SEM, if such grounding is not provided electrons emitted by the electron beam accumulate on the surface that is being inspected causing severe distortions of this surface. Earlier SEM's were provided with relatively small chambers, which limited inspection to relatively small specimens. These specimens were typically mounted onto an aluminum pedestal using a conductive silver paste. Dependent on the type of surface that is being examined, this method can create considerable image distortion as a result of particle creation and distribution throughout the chamber. High resolution for this method of surface examination required high-energy beam accelerating voltages, further aggravating the problem of particle creation and thus image distortion. This problem has been addressed by disposing a thin layer of gold onto the surface that is being examined, thus providing a good conductive layer over this surface and thereby significantly improving surface resolution.
Current technology allows for the inspection of larger surfaces that can be inserted into the SEM. This method however remains t

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