Abrading – Abrading process – Glass or stone abrading
Reexamination Certificate
2000-08-03
2002-09-24
Morgan, Eileen P. (Department: 3723)
Abrading
Abrading process
Glass or stone abrading
C451S036000, C451S285000, C451S526000
Reexamination Certificate
active
06454634
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to improved polishing pads used to polish and/or planarize substrates, particularly metal or metal-containing substrates during the manufacture of a semiconductor device. Specifically, this invention relates to pads having an optimized combination of physical properties for improved pad performance.
DISCUSSION OF THE PRIOR ART
Chemical-mechanical planarization (“CMP”) is a process currently practiced in the semiconductor industry for the production of flat surfaces on integrated circuits devices. This process is discussed in “
Chemical Mechanical Planarization of Microelectronic Materials
”, J. M. Steigerwald, S. P. Murarka, R. J. Gutman, Wiley, 1997, which is hereby incorporated by reference in its entirety for all useful purposes. Broadly speaking, CMP involves flowing or otherwise placing a polishing slurry or fluid between an integrated circuit device precursor and a polishing pad, and moving the pad and device relative to one another while biasing the device and pad together. Such polishing is often used to planarize: i. insulating layers, such as silicon oxide; and/or ii. metal layers, such as tungsten, aluminum, or copper.
As semiconductor devices become increasingly complex (requiring finer feature geometries and greater numbers of metallization layers), CMP must generally meet more demanding performance standards. A relatively recent CMP process has been the fabrication of metal interconnects by the metal damascene process (see for example, S. P. Murarka, J. Steigerwald, and R. J. Gutmann, “
Inlaid Copper Multilevel Interconnections Using Planarization by Chemical Mechanical Polishing
”, MRS Bulletin, pp. 46-51, June 1993, which is hereby incorporated by reference in its entirety for all useful purposes).
With damascene-type polishing, the polished substrate is generally a composite rather than a homogenous layer and generally comprises the following basic steps: i. a series of metal conductor areas (plugs and lines) are photolithographically defined on an insulator surface; ii. the exposed insulator surface is then etched away to a desired depth; iii. after removal of the photoresist, adhesion layers and diffusion barrier layers are applied; iv. thereafter, a thick layer of conductive metal is deposited, extending above the surface of the insulator material of the plugs and lines; and v. the metal surface is then polished down to the underlying insulator surface to thereby produce discrete conductive plugs and lines separated by insulator material.
In the ideal case after polishing, the conductive plugs and lines are perfectly planar and are of equal cross-sectional thickness in all cases. In practice, significant differences in thickness across the width of the metal structure can occur, with the center of the feature often having less thickness than the edges. This effect, commonly referred to as “dishing”, is generally undesirable as the variation in cross-sectional area of the conductive structures can lead to variations in electrical resistance. Dishing arises because the harder insulating layer (surrounding the softer metal conductor features) polishes at a slower rate than the metal features. Therefore, as the insulating region is polished flat, the polishing pad tends to erode away conductor material, predominantly from the center of the metal feature, which in turn can harm the performance of the final semiconductor device.
SUMMARY OF THE INVENTION
The present invention is directed to polishing pads for CMP having low elastic recovery during polishing, while also exhibiting significant anelastic properties relative to many known polishing pads. In some embodiments, the pads of the present invention further define: i. a surface roughness of about 1 to about 9 microns Ra; ii. a hardness of about 40 to about 70 Shore D; and iii. a tensile Modulus up to about 2000 MPa at 40° C. In one embodiment, the polishing pads of the present invention define a ratio of E′ at 30° and 90° C. being less than about 5, preferably less than about 4.6 and more preferably less than about 3.5. In other embodiments of the present invention, the polishing pad defines a ratio of E′ at 30° C. and 90° C. from about 1.0 to about 5.0 and a KEL from about 100 to about 1000 (1/Pa) (40° C.). In other embodiments, the polishing pad has a surface roughness of about 2 to about 7 micron Ra, a hardness of about 45 to about 65 Shore D, a Modulus E′ of about 150 to about 1500 MPa at 40° C., a KEL of about 125 to about 850 (1/Pa at 40° C.) and a ratio of E′ at 30° C. and 90° C. of about 1.0 to about 4.0. In yet other embodiments, the polishing pads of the present invention have a surface roughness of about 3 to about 5 micron Ra, a hardness of about 55 to about 63 Shore D, a Modulus E′ of 200 to 800 MPa at 40° C., KEL of 150 to 400 (1/Pa at 40° C.) and a ratio of E′ at 30° C. and 90° C. of 1.0 to 3.5.
In one embodiment, the modulus value can be as low as about 100 MPa, provided the pad is (sufficiently) hydrolytically stable. Such stability is characterized by substantially stable pad performance as the pad is increasingly subjected to water based fluids.
In other embodiments, the present invention is directed to a process for polishing metal damascene structures on a semiconductor wafer by: i. pressing the wafer against the surface of a pad in combination with an aqueous-based liquid that optionally contains sub-micron particles; and ii. providing mechanical or similar-type movement for relative motion of wafer and polishing pad under pressure so that the moving pressurized contact results in planar removal of the surface of said wafer.
DESCRIPTION OF THE INVENTION
The preferred pads of the present invention are characterized by high-energy dissipation, particularly during compression, coupled with high pad stiffness. Preferably, the pad exhibits a stable morphology that can be reproduced easily and consistently. Furthermore, the pad surface preferably resists glazing, thereby requiring less frequent and less aggressive conditioning and resulting in low pad wear and longer pad life. In one embodiment, the polishing pads of the present invention exhibit low dishing of metal features, low oxide erosion, reduced pad conditioning, high metal removal rates, good planarization, and/or lower defectivity (scratches and light point defects), relative to known polishing pads.
The pads of the present invention can be made in any one of a number of different ways. Indeed, the exact composition generally is not important so long as the pads exhibit low elastic recovery during polishing. Although urethanes are a preferred pad material, the present invention is not limited to polyurethanes and can comprise virtually any chemistry capable of providing the low elastic recovery described herein. The pads can be, but are not limited to, thermoplastics or thermosets and can be filled or unfilled. The pads of the present invention can be made by any one of a number of polymer processing methods, such as but not limited to, casting, molding, coating, extruding, photoimaging, printing, sintering, and the like.
In a preferred embodiment, the pads of the present invention have one or more of the following attributes:
1. Dishing of conductive features such as conductors and plugs is minimal,
2. Die-level planarity is achieved across the wafer surface, and/or
3. Defects such as scratches and light-point-defects are minimal and do not adversely effect electrical performance of the semiconductor device.
The above attributes can be influenced and sometimes controlled through the physical properties of the polishing pad, although pad performance is also dependent on all aspects of the polishing process and the interactions between pad, slurry, polishing tool, and polishing conditions, etc.
In one embodiment, the pads of the present invention define a polishing surface which is smooth, while still maintaining micro-channels for slurry flow and nano-asperities to promote polishing. One way to minimize pad roughness is to construct an
Burke Peter A.
Cook Lee Melbourne
James David B.
Shidner David
Vishwanathan Arun
Benson Kenneth A.
Kaeding Konrad
Kita Gerald K.
Morgan Eileen P.
Rodel Holdings Inc.
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