Abrading – Flexible-member tool – per se – Interrupted or composite work face
Utility Patent
1997-08-25
2001-01-02
Banks, Derris H. (Department: 3723)
Abrading
Flexible-member tool, per se
Interrupted or composite work face
C451S285000
Utility Patent
active
06168508
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a modified polishing pad design for use in chemical-mechanical polishing (sometimes referred to in the art as “CMP”) of integrated circuits (ICs). More particularly, the present invention relates to a polishing pad having a surface, which includes at least two different polishing areas that contact a substantial portion of a wafer surface during chemical-mechanical polishing (CMP) to produce a more uniformly polished and a more planar integrated circuit (IC) surface.
CMP typically involves mounting an IC, such as a semiconductor wafer, face down on a holder and rotating the wafer face against a polishing pad mounted on a platen, which in turn rotates or orbits about an axis. A slurry containing a chemical that chemically interacts with the facing wafer layer and an abrasive that physically removes that layer is flowed between the wafer and the polishing pad or on the pad near the wafer.
In semiconductor wafer fabrication, this technique is commonly applied to planarize various wafer layers such as dielectric layers, metallization layers, etc. By way of example, by subjecting a blanket deposited metal layer on the wafer surface to CMP, the metal layer on a dielectric surface is removed and the metal layer remaining inside a contact hole or a via forms a metal plug inside the dielectric layer. As is well known in the art, contact holes and vias are openings in the dielectric layer that surround a contact to an underlying substrate layer or a metallization layer, respectively, disposed below the dielectric surface.
Polishing pads used in CMP have different characteristics, such as hardness, specific gravity, compressibility, etc., which offer different advantages and are therefore employed in different applications. Unfortunately, these advantages are typically realized at the expense of other undesirable effects. By way of example, a polishing pad made from a hard material, such as polyurethane, offers better planarity of the wafer surface and a high film removal rate at the expense of producing a highly scratched wafer surface, which often requires further polishing on a soft polishing pad in a separate buffing or fine polishing step. This translates into a lower wafer throughput for the wafer CMP process.
As another example, a polishing pad made from a soft material, such as polyurethane impregnated felt, conforms to the wafer surface to a greater extent than a hard polishing pad and produces a relatively scratch-free and uniformly polished wafer surface, which is realized at the expense of slow film removal rate and “dishing” on some local feaatures of the wafer surface. The undesirable result of dishing is explained hereinafter in the context of tungsten CMP to form tungsten plugs. As used herein, the terms “uniform” and “uniformly polished,” and variation thereon refer to local flatness assessed at individual die on a wafer surface. In contrast, “planar” surfaces are flat over the entire wafer surface (spanning multiple die). Thus, while a particular polishing system may produce a highly “uniform” surface (as determined by evaluating individual die), it may produce a particularly non-planar surface. In other polishing systems, the opposite may be true.
Film removal during tungsten CMP is more of a chemical process than a mechanical process. The slurry introduced on the polishing pad surface during CMP includes a reactive component, e.g., an oxidizing agent, and abrasive particles. Basically, the oxidizing agent which may be ferric nitrate (Fe(NO
3
)
3
) reacts with the tungsten to form tungsten oxide, which is abraded during CMP by the action of abrasive particles that typically include silica or alumina particles. The soft polishing pad is desirable for film removal in this context because it acts like a sponge and under pressure during wafer CMP, it almost uniformly releases the absorbed slurry on the wafer surface. As a result, the tungsten layer is nearly uniformly oxidized throughout the wafer surface and a uniform film removal rate is realized. Upon inspection of the tungsten plug surface, after CMP, under a microscope, however, formation of an indentation or a recess shaped like a dish is observed on the tungsten plug surface. Thus, the tungsten plug surface is referred to as suffering from dishing. Dishing is undesirable because it lowers the conductivity of the plug and sometimes to the point of causing a catastrophic device failure.
In order to offset the effects of dishing, the wafer surface is subjected to buffing or fine polishing, in a separate step after (coarse) CMP, typically on an even softer polishing pad. During fine polishing, a slurry composition tailored to remove the dielectric layer surrounding the plug is introduced so that after fine polishing, the plug protrudes slightly above the dielectric layer surface. Thus, the fine polishing step that follows the (coarse) CMP step corrects for dishing of the tungsten plug surface. As mentioned before, the additional fine polishing step lowers the throughput of the wafer CMP process.
What is therefore needed is a polishing pad that provides the advantages of the conventional polishing pad materials without incurring the expense of their undesirable effects.
SUMMARY OF THE INVENTION
To achieve the foregoing, the present invention provides a polishing pad for chemical-mechanical polishing of an integrated circuit surface. The polishing pad includes: (1) a first polishing area having a first value of a physical property; and (2) a second polishing area having a second value of the physical property which second value is different from the first value, such that during chemical-mechanical polishing of an integrated circuit surface, the integrated circuit rotates and oscillates on the polishing pad so that a substantial portion of the integrated circuit surface contacts both the first and second polishing areas, wherein a width of the first and second polishing areas is greater than about 40 mils.
The width of the first and second polishing areas preferably ranges from about 0.08 and about 3 inches and more preferably ranges from about 0.25 and about 3 inches. Microgrooves and microgrooves, in contrast, have a much smaller width, e.g., about 15 and about 40 mils, compared to the width of first and second polishing areas.
The term “physical property” of an area on the polishing pad refers to such surface characteristics as hardness, specific gravity, compressibility, abrasiveness, the height of the polishing area, etc. The first polishing area may have a hardness that is greater than the second polishing area. The rockwell hardness of the first polishing area may be between about 30 and about 90 Shore A.
The first polishing area may be more compressible than the second polishing area. The compressibility of the first polishing area is between about 2 and about 50%. The specific gravity of the first polishing area is between about 0.6 and about 1.5.
The first polishing area may include abrasive particles and the second polishing area may not include abrasive particles. The first polishing area may protrude from a surface of the polishing pad and relative to the second polishing area. The first polishing area may protrude relative to the second polishing area by a distance that ranges from between about 5 mils to about 100 mils. The first and second polishing areas includes at least one material selected from the group consisting of polyurethane, urethane, polymer, polyurethane impregnated felt, abrasive and filler material.
In another aspect, the present invention provides a polishing pad for chemical-mechanical polishing of an integrated circuit surface. The polishing pad includes (1) a center polishing area disposed towards a center of a surface of the polishing pad and having a first value of a physical property, (2) a peripheral polishing area located at the edge of the polishing pad having the first value of the physical property; and (3) a ring shaped polishing area defined by an inner boundary and an outer boundary and located between the center p
Lee Dawn M.
Nagahara Ronald J.
Banks Derris H.
LSI Logic Corporation
LandOfFree
Polishing pad surface for improved process control does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Polishing pad surface for improved process control, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Polishing pad surface for improved process control will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2551844