Polishing pad and polishing device

Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means

Reexamination Certificate

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C438S690000, C438S959000, C438S693000, C216S002000, C216S038000, C216S088000, C216S089000, C216S099000, C451S017000, C451S041000, C451S286000, C451S287000, C451S288000, C451S526000, C451S527000

Reexamination Certificate

active

06362107

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a semiconductor substrate polishing device and polishing pad; more particularly, it relates to a polishing device and a polishing pad for the mechanical planarization of the surface of insulating layers and the surface of metal interconnects formed on a silicon or other semiconductor substrate.
TECHNICAL BACKGROUND
Year by year, there are ever greater levels of integration in large scale integrated circuits (LSI) typified by semiconductor memories and, along with this, large scale integrated circuit production technology is providing ever greater packaging densities. Moreover, together with such increasingly high densities, the number of semiconductor device layers is also increasing. As a result of this increase in the number of layers, while not hitherto being an issue, the unevenness in the semiconductor wafer main face produced by such layering has become a problem. For example, as described in Nikkei Microdevice, July 1994, pages 50-57, the planarization of the semiconductor wafer using chemical mechanical polishing (CMC) techniques is being investigated with the objective of dealing with the inadequate depth of focus at the time of light exposure due to the unevenness produced by layering, or with the objective of raising interconnect densities by planarizing through-hole regions.
Generally speaking, CMP equipment is composed of a polishing head for holding the semiconductor substrate, which is the material undergoing treatment, a polishing pad for carrying out polishing of the material undergoing treatment, and a polishing platen for holding this polishing pad. In the semiconductor substrate polishing treatment, a slurry comprising polishing agent and chemical liquid is used and, by effecting relative motion between the semiconductor substrate and the polishing pad, the semiconductor substrate surface layer is smoothened. In the case, for example, of a silicon dioxide (SiO
2
) film formed on a main face of the semiconductor substrate, the polishing rate at the time of this semiconductor substrate polishing process is roughly proportional to the relative velocity between semiconductor substrate and polishing pad, and the load. Hence, in order to bring about uniform polishing of each region of the semiconductor substrate, it is necessary to make the load applied to the semiconductor substrate uniform.
However, there are often variations in level over the entire surface of the semiconductor substrate held on the polishing head, due to inherent curvatures and other such variations in shape. Hence, it is desirable that there be used a soft polishing pad in order to apply a uniform load to each region of the semiconductor substrate. However, when a polishing process is carried out using a soft polishing pad, the planarity of the semiconductor substrate surface local unevenness is impaired. For example, the problem arises that in parts unevenness of the aforesaid semiconductor substrate surface layer is rounded by the polishing, that is to say the polished face is rounded and not made planar. In contrast, in the case where the polishing of the semiconductor substrate is carried out in the same way using a hard polishing pad then, while it is possible to enhance the planarity of the semiconductor substrate surface local unevenness unlike in the case of using a soft polishing pad, the hard polishing pad is unsatisfactory from the point of view of adapting to overall variations in level at the semiconductor substrate. For example, uneven regions of the semiconductor substrate surface where undulations project outwards are considerably polished, but uneven regions where such undulations are depressed are largely unpolished and remain as they are. Such non-uniform polishing leads to exposure of the aluminium interconnects and local variations in the thickness of the silicon dioxide insulating film following polishing and, for example, through-hole diameter irregularities and the fact that planarization of unevenness due to layer superposition is not possible, cause inadequate depth of focus at the time of light exposure.
With regard to the prior-art relating to polishing pads aimed at satisfying the opposing demands of enhancing such local planarity and overall adaptability, a two layer pad has been tried as described in JP-A-6-21028. The two layer pad described in JP-A-6-21028 has a construction where the polishing layer which directly contacts the semiconductor substrate is supported on a cushioning layer of bulk modulus no more than 250 psi/psi within the stress range 4 psi to 20 psi, and the polishing layer has a bulk modulus greater than this. The objective is that the cushioning layer absorbs overall variations in level on the semiconductor substrate, while the polishing layer is resistant to curvature over more than a certain area (for example more than the die spacing). However, with this conventional two-layer pad, the following problems still remain in terms of polishing performance. Firstly, even though the bulk modulus of the polishing layer is greater than the bulk modulus of the cushioning layer, the local planarity of the semiconductor substrate surface may still be impaired, and there is not necessarily a correlation between local planarity and the bulk modulus of the polishing layer. Secondly, since the bulk modulus of the cushioning layer is no more than 250 psi/psi within the stress range 4 psi to 20 psi, there is poor adaptability to variations in level over the semiconductor substrate as a whole, with the result that there is not obtained sufficient uniformity of planarity over the entire face of the semiconductor substrate. Furthermore, as stated on pages 177-183 of CMP Science by Science Forum Publishing (Co.), it has not been possible to fully resolve the question of how close to the edge within the wafer face is the required planarization to be carried out. Thirdly, if the rate of rotation of the polishing platen is high, the planarity is good but there is the problem that adaptability to the variations in level over the entire semiconductor substrate face is made worse. Consequently, an improved polishing device or polishing pad is required to overcome the above problems.
DISCLOSURE OF THE INVENTION
The objective of the present invention lies in offering a means for uniformly planarizing the entire face of a semiconductor substrate, in the case of a polishing device or a polishing pad employed in a mechanical planarizing process in which the surface of insulating layers or metal interconnects formed on a semiconductor substrate are smoothened by polishing. Specifically, this invention relates to “a polishing pad which is characterized in that it has a polishing layer of rubber A-type microhardness of at least 80° and a cushioning layer of bulk modulus at least 40 MPa and tensile modulus in the range 0.1 MPa to 20 MPa”
and
“a method of polishing a semiconductor substrate which is characterized in that the semiconductor substrate is fixed to a polishing head, and the semiconductor substrate is polished by rotating said polishing head or a polishing platen, or both, in a state where there is pressed against the semiconductor substrate a polishing layer of rubber A-type microhardness at least 80° affixed to the polishing platen via a cushioning layer of bulk modulus at least 40 MPa and tensile modulus 0.1 MPa to 20 MPa”
and also
“a polishing device which is characterized in that it is a polishing device equipped with a polishing head, a polishing pad which confronts the polishing head, a polishing platen to which the polishing pad is fixed, and a means for rotating the polishing head, the polishing platen or both of these, and where the polishing pad contains a cushioning layer of bulk modulus at least 40 MPa and tensile modulus in the range 0.1 to 20 MPa and, in the direction of the polishing head, a polishing layer of rubber A-type microhardness at least 80° ”.
OPTIMUM MODE FOR PRACTISING THE INVENTION
Below, the mode of practising the invention is explained. The cushioning layer in the present invention need

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