Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2001-09-12
2003-03-11
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
Reexamination Certificate
active
06531399
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a technique for polishing the surface of a workpiece, and more particularly to a polishing method that can be suitably applied to planarization of a silicon wafer surface in a semiconductor manufacturing process.
2. Description of the Related Art
In a manufacturing process for fabricating a high density semiconductor integrated circuit element on the surface of a silicon wafer, steps are formed on the surface of the silicon wafer by the formation of a dielectric film, a metallic pattern or the like. If pattern formation is further carried out over the silicon wafer having the steps formed on the surface, for example, the depth of focus in lithography is caused to decrease, so that there is caused a drawback that a resolution becomes insufficient. For this reason, the wafer process employs a chemical mechanical polishing (CMP) technique for planarizing the steps of the device fabrication.
At the polishing step in the device fabrication, usually, a removal per unit time (hereinafter referred to as a removal rate) is periodically measured for grasping the degradation of the wafer polishing efficiency depending on the loss of sufficient surface roughness of the polishing pads or the like. More specifically, every time a predetermined number of silicon wafers are polished, a dummy wafer is polished, to detect a ratio m/T of a change m in a thickness of a silicon dioxide film formed on the surface of the dummy wafer (a difference in thickness obtained before and after the polishing) to a polishing time T, as a removal rate.
At the polishing step in the device fabrication, a value obtained by dividing a target removal by a removal rate thus calculated periodically is set to be a polishing time per silicon wafer. Consequently, there can be prevented a fluctuation in the removal caused by a deterioration in the polishing efficiency of a polishing pad. Further, when the removal rate comes to be smaller than a predetermined value during the polishing, the surface of the polishing pad (a surface used for polishing the silicon wafer) is dressed through a diamond disk or the like, so as to recover the polishing efficiency of the polishing pad which is deteriorated by the loss of sufficient surface roughness of the polishing pads or the like. A fluctuation in the removal rate can be therefore suppressed.
By a process utilizing the removal rate periodically calculated during the polishing, a fluctuation in the removal rate is suppressed and the time required for polishing the wafer is controlled depending on the removal rate. Therefore, the error of the removal from the wafer can be prevented.
In the periodic measurement of the removal rate utilizing the dummy wafer, it is difficult to make real-time detection of the removal rate which successively changes during the polishing. For this reason, it is possible to miss the optimum timing of a dressing process and the optimum timing of a process for correcting the time required for polishing might. Moreover, while the removal rate is measured through the dummy wafer, the polishing process of the wafer is interrupted, so that the manufacturing efficiency of a semiconductor device decreases to that extent.
SUMMARY OF THE INVENTION
The present invention provides a method of polishing workpieces, comprising the steps of:
relatively moving a polishing tool and a workpiece while causing the polishing tool and the workpiece to be in contact with each other, to polish the workpiece;
successively measuring a friction caused between the workpiece and the polishing tool during the polishing;
quantifying a characteristic of the polishing tool related to polishing efficiency of the polishing tool on the basis of on the friction when the friction is measured at the measuring step;
deciding whether or not a value obtained by quantification in the quantifying step is smaller than a predetermined reference value; and
dressing the polishing tool when it is decided that that the value is smaller than the reference value in the deciding step.
REFERENCES:
patent: 5743784 (1998-04-01), Birang et al.
patent: 6224464 (2001-05-01), Nojo
patent: 6306008 (2001-10-01), Moore
patent: 6306009 (2001-10-01), Sandhu et al.
patent: 10-315124 (1998-12-01), None
Kojima Hiroyuki
Ohkawa Tetsuo
Sato Hidemi
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Niebling John F.
Stevenson André C
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