Abrasive tool making process – material – or composition – With inorganic material – Clay – silica – or silicate
Reexamination Certificate
2002-10-04
2003-05-20
Marcheschi, Michael (Department: 1755)
Abrasive tool making process, material, or composition
With inorganic material
Clay, silica, or silicate
C106S003000, C438S692000, C438S693000, C216S106000, C216S108000
Reexamination Certificate
active
06565619
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a polishing composition to be used for polishing for planarization of the surface of a semiconductor. More particularly, it relates to a polishing composition which provides excellent planarization characteristics in polishing for planarization of the surface of a semiconductor device comprising copper, a tantalum-containing compound and a low dielectric constant insulating material and which is useful for forming an excellent polished surface, and to a polishing method employing such a polishing composition.
2. Discussion of Background
Progress of computer products has been remarkable in recent years, and parts to be used for such products, such as ULSI devices, have been developed for high integration and high speed, year after year. Along with such progress, the design rule for semiconductor devices has been progressively refined year after year, the depth of focus in a process for producing devices tends to be shallow, and planarization required for the pattern-forming surface tends to be increasingly severe.
Further, to cope with an increase in resistance of the wiring and the parastic capacity due to refinement of the wiring, it has been studied to employ copper instead of tungsten or aluminum, as the wiring material. On the other hand, as an insulating material, it has been studied to use a low dielectric constant insulating material (commonly called “Low-k material”) instead of silicon dioxide or silicon oxyfluoride.
When copper is used as the wiring material, copper is hardly processable by anisotropic etching by its nature, and accordingly, it requires the following process.
Namely, after forming wiring grooves and vias on an insulating layer, copper wirings are formed by sputtering or plating (so-called damascene method), and then an unnecessary copper layer deposited on the insulating layer is removed by mechanochemical polishing (Chemical Mechanical Polishing, hereinafter referred to as “CMP”) which is a combination of mechanical polishing and chemical polishing.
However, in such a process, it may happen that copper atoms will diffuse into the insulating layer to deteriorate the device properties. Therefore, for the purpose of preventing diffusion of copper atoms, it has been studied to provide a barrier layer on the insulating layer having wiring grooves or vias formed. As a material for such a barrier layer, metal tantalum or a tantalum-containing compound including tantalum nitride, is most suitable from the viewpoint of the reliability of the device and is expected to be employed mostly in the future. For the purpose of the present invention, “a tantalum-containing compound” includes metal tantalum in addition to tantalum nitride, etc., and “copper” includes an alloy of copper with aluminum or the like.
As common Low-k materials to be used as insulating materials, “Black Diamond” (tradename, manufactured by Applied Materials) and “CORAL” (tradename, manufactured by Novellus Systems) may, for example, be mentioned as CVD type materials, and “SiLK” (tradename, manufactured by the Dow Chemical), “FLARE” (tradename, manufactured by Honeywall Electronic Materials) and their porous materials, may, for example, be mentioned as coating type materials. These materials are expected to be used in future.
Accordingly, in such a CMP process for a semiconductor device containing such copper, tantalum-containing compound and Low-k material, firstly the copper (the copper layer) as the outermost layer and then, the tantalum-containing compound (the tantalum-containing compound layer) as the barrier layer, are polished, respectively, and polishing will be completed when it has reached the Low-k material (the Low-k layer).
The above CMP process for forming a semiconductor device containing the above copper, tantalum-containing compound and Low-k material, is carried out usually by a two step polishing process. Namely, firstly, only the copper layer is polished by a first step polishing, and then, the tantalum-containing compound layer and the Low-k layer are simultaneously polished by a second step polishing. For this process, the following two methods are conceivable depending upon the manner of termination of the first step polishing. Firstly, only the copper layer is polished by the first step polishing, and this can be done by two methods i.e. {circle around (1)} a method wherein the polishing is terminated before reaching to the barrier layer (the tantalum-containing compound layer) while the copper layer of from 1,000 to 2,000 Å still remains, and {circle around (2)} a method wherein all of the copper layer to be removed is polished and removed, and the polishing is completed after reaching the barrier layer (the tantalum-containing compound layer). When polishing is carried out by the above method {circle around (2)}, on completion of the first step polishing, dishing or erosion is likely to be observed at the copper wiring portion. In order to obtain a polished surface free from such dishing or erosion, it is advisable to terminate the first step polishing by the above method {circle around (1)} and then to carry out a step of polishing the remaining copper layer simultaneously together with the tantalum-containing compound layer and the Low-k layer at the same stock removal rate by the second step polishing.
Here, “dishing” means that the copper wiring after polishing is recessed as compared with the Low-k layer, and “erosion” means that a densely wired portion is recessed as compared with other portions.
With respect to the above polishing composition for the first step polishing, JP-A-7-233485 discloses a polishing liquid for a copper type metal layer, which comprises at least one organic acid selected from aminoacetic acid and amidesulfuric acid, an oxidizing agent and water, and a method for producing a semiconductor device using such a polishing liquid.
When this polishing liquid is used for polishing a copper layer, a relatively high stock removal rate (usually at a level of 5,000 Å/min) can be obtained. It is considered that copper atoms on the copper layer surface become copper ions by the action of the oxidizing agent, and such copper ions are taken by said at least one organic acid selected from aminoacetic acid and amidesulfuric acid, whereby a high stock removal rate can be obtained. This polishing composition is useful as a polishing composition for the first step polishing i.e. as a polishing composition for the purpose of polishing a copper layer at a high stock removal rate.
On the other hand, with respect to a polishing composition for the second step polishing, the present inventors have already proposed a polishing composition comprising an abrasive, an oxidizing agent capable of oxidizing tantalum, a reducing agent capable of reducing tantalum oxide, and water, and a polishing method employing it (JP-A-2000-160139), and, as a first improvement thereof, a polishing composition comprising an abrasive, oxalic acid, an ethylene diamine derivative, a benzotriazole derivative and water, as well as a polishing composition comprising an abrasive, oxalic acid, an ethylene diamine derivative, a benzotriazole derivative, hydrogen peroxide and water (JP-A-2001-89747). These inventions relate to polishing compositions useful for a case where silicon dioxide or silicon oxyfluoride is used as an insulating material.
However, when such conventional polishing compositions are used for polishing of a Low-k material, it has been very difficult to polish the Low-k material at a sufficient stock removal rate. Therefore, it has been difficult to polish copper, a tantalum-containing compound and a Low-k material at the same and high stock removal rate. Accordingly, it has been desired to have a polishing composition suitable for such a process developed.
SUMMARY OF THE INVENTION
The present invention has been made to solve the above-mentioned problem and to provide a polishing composition capable of polishing copper, a tantalum-containing compound and a Low-k material at a
Asano Hiroshi
Ina Katsuyoshi
Sakai Kenji
Fujimi Incorporated
Marcheschi Michael
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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