Abrasive tool making process – material – or composition – With inorganic material – Clay – silica – or silicate
Reexamination Certificate
2000-02-11
2002-03-12
Marcheschi, Michael (Department: 1755)
Abrasive tool making process, material, or composition
With inorganic material
Clay, silica, or silicate
C106S003000
Reexamination Certificate
active
06355075
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a polishing composition to be used for polishing to planarize the surface of semiconductors. More particularly, it relates to a polishing composition useful for forming an excellent polished surface having an excellent planarization characteristic in polishing for planarization of the surface containing copper and tantalum or a tantalum-containing compound.
2. Discussion of Background
Progress of so-called high technology products including computers has been remarkable in recent years, and parts to be used for such products, such as ULSI, have been developed for high integration and high speed, year after year. Along with such progress, the design rule for semiconductor devices has been progressively refined year after year, the depth of focus in a process for producing devices tends to be shallow, and planarization required for the pattern-forming surface tends to be increasingly severe.
Further, various attempts have been made to improve the efficiency of the polishing process for semiconductor devices. For example, U.S. Pat. Nos. 5,391,258 and 5,476,606 disclose a composition for polishing a composite material comprising a metal and silica, particularly optimum selectivity for removal of the respective materials. In these patents, it is primarily intended to improve the selectivity for removal as between tungsten and silica by suppressing the rate of removal of silica.
Further, in recent years, to cope with an increase in resistance of the wiring due to refinement of the wiring, it has been studied to employ copper wiring instead of tungsten wiring and aluminum wiring, as the wiring material. By its nature, copper is hardly processable by etching, and accordingly, it requires the following process. Namely, after forming wiring grooves and perforations on an insulating layer, copper wirings are formed by sputtering or plating, and then an unnecessary copper layer deposited on the insulating layer is removed by chemical mechanical polishing (hereinafter referred to as CMP) which is a combination of mechanical polishing and chemical polishing.
However, in such a process, it may happen that copper atoms will diffuse into the insulating layer to deteriorate the device properties. Therefore, for the purpose of preventing diffusion of copper atoms, it has been proposed to provide a barrier layer on the insulating layer having wiring grooves or perforations formed. As a material for such a barrier layer, tantalum or tantalum nitride (hereinafter will generally be referred to as a tantalum-containing compound) is most suitable also from the viewpoint of the reliability of the device and is expected to be employed mostly in the future.
Accordingly, in such a CMP process for a semiconductor device containing such a copper layer and a tantalum-containing compound, firstly the copper layer as the outermost layer and then the tantalum-containing compound layer as the barrier layer, are polished, respectively, and polishing will be completed when it has reached the insulating layer of e.g. silicon dioxide or silicon trifluoride.
In such a CMP process for forming copper wirings, the following problems exist. Namely, the most serious problem may be such that the copper wirings after polishing are recessed as compared with the insulating layer (so-called dishing), and a portion where wirings are densely formed, is recessed as compared with other portions (so-called erosion). As an ideal process, it is desired that by using only one type of a polishing composition, the copper layer and the tantalum-containing compound layer are uniformly removed by polishing in a single polishing step, and polishing will be completed certainly when it has reached the insulating layer.
With respect to copper wirings in a multi-layer structure, practicality is desired with respect to all of the copper wiring layers. Namely, in the case of the uppermost layer, the thickness of the copper layer may be as thick as 2 &mgr;m (20,000 A), and in the case of the lowermost layer, the thickness of the copper layer may be at a level of 3,000 A. Whereas, the thicknesses of tantalum-containing compound layers as barrier layers are substantially the same for all layers at a level of from 200 to 500 A. Under these circumstances, it has been necessary to adopt separate processes for copper wirings in the upper layers and copper wirings in the lower layers.
Namely, for copper wirings in an upper layer, a conventional so-called two step polishing process is effective. In this process, firstly, in the first polishing, only the copper layer is polished at a high stock removal rate (usually at least 5,000 A/min). With respect to the terminal point of polishing, there are two methods, i.e. {circle around (1)} a method in which the polishing is terminated prior to reaching the barrier layer while the copper layer still remains in a thickness of from 1,000 to 2,000 A, and {circle around (2)} a method wherein the polishing is terminated when the copper layer to be removed, has all been removed and the barrier layer has been reached. In either method, the performance required for the first polishing is a high stock removal rate of the copper layer. On the other hand, the performance required for the second polishing is a high stock removal rate of the barrier layer and suppression of the stock removal rate of the insulating layer.
With respect to the polishing composition to be used in the first polishing of this two step polishing process, for example, JP-A-07-233485 discloses a polishing liquid for a copper type metal layer, which comprises at least one organic acid selected from the group consisting of aminoacetic acid and amidosulfuric acid, an oxidizing agent and water, and a method for producing a semiconductor device using such a polishing liquid.
If this polishing liquid is used for polishing a copper layer, a relatively high stock removal rate (usually about 5,000 A/min) is obtainable. It is believed that copper atoms on the copper layer surface become copper ions, and such copper ions are taken into a chelate compound, whereby a high stock removal rate can be obtained. Such a polishing composition is considered to be useful for the first polishing in forming copper wirings for the upper layer.
However, an ideal polishing composition which is useful for polishing a tantalum-containing compound layer i.e. for the second polishing, has not heretofore been proposed for the CMP process based on the above concept. Under these circumstances, the present inventors have previously proposed a polishing composition comprising an abrasive, an oxidizing agent capable of oxidizing tantalum, a reducing agent capable of reducing tantalum oxide and water, and a polishing method employing it (JP10-342106). Further , as improvements of this composition, the present inventors have proposed a polishing composition comprising an abrasive, oxalic acid, an ethylenediamine derivative, a benzotriazole derivative and water, and a polishing composition comprising an abrasive, oxalic acid, an ethylenediamine derivative, a benzotriazole derivative, hydrogen peroxide and water (JP11-266049). By this invention, a tantalum-containing compound can be polished certainly at a high stock removal rate, and these polishing compositions can be used for the second polishing.
When the above polishing compositions are used for polishing, a stock removal rate against a tantalum-containing compound can be accomplished to some extent. However, the ratio of the rate of removal of the tantalum-containing compound to the rate of removal of the insulating layer (hereinafter referred to simply as the selectivity ratio) is about 4 at best, whereby the process margin is narrow to certainly stop the polishing by the insulating layer, and consequently, the yield used to be low. Namely, it has been desired to develop a polishing composition which has a high stock removal rate against the barrier layer and which is capable of further suppressing the stock removal rate against the insulating laye
Hori Tetsuji
Ina Katsuyoshi
Rader W. Scott
Shemo David M.
Fujimi Incorporated
Marcheschi Michael
LandOfFree
Polishing composition does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Polishing composition, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Polishing composition will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2833999