Polish pad with non-uniform groove depth to improve wafer...

Details Polish pad with non-uniform groove depth to improve wafer... Polish pad with non-uniform groove depth to improve wafer...

2005-10-04

2005-10-04

Hail, III, Joseph J. (Department: 3723)

Abrading

Abrading process

Glass or stone abrading

C451S526000, C451S527000, C451S528000, C451S529000, C451S530000, C451S532000

Reexamination Certificate

active

06951506

ABSTRACT:
The present invention describes a method for creating a differential polish rate across a semiconductor wafer. The profile or topography of the semiconductor wafer is determined by locating the high points and low points of the wafer profile. The groove pattern of a polish pad is then adjusted to optimize the polish rate with respect to the particular wafer profile. By increasing the groove depth, width, and/or density of the groove pattern of the polish pad the polish rate may be increased in the areas that correspond to the high points of the wafer profile. By decreasing the groove depth, width, and/or density of the groove pattern of the polish pad the polish rate may be decreased in the areas that correspond to the low points of the wafer profile. A combination of these effects may be desirable in order to stabilize the polish rate across the wafer surface in order to improve the planarization of the polishing process.

REFERENCES:
patent: 5297364 (1994-03-01), Tuttle
patent: 5645469 (1997-07-01), Burke et al.
patent: 5665249 (1997-09-01), Burke et al.
patent: 5730642 (1998-03-01), Sandhu
patent: 6099394 (2000-08-01), James et al.
patent: 6110832 (2000-08-01), Morgan, III et al.
patent: 6824455 (2004-11-01), Osterheld et al.

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