Polish method for semiconductor device planarization

Details Polish method for semiconductor device planarization Polish method for semiconductor device planarization

2007-02-06

2007-02-06

Nguyen, Ha Tran (Department: 2812)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S787000, C438S791000

Reexamination Certificate

active

10384641

ABSTRACT:
A polish method for planarization is disclosed. The method uses a combination of a traditional oxide CMP and HSP-CMP (High Selectivity and Planarization) with a fix abrasive pad to meet the requirements of the CMP process for a device feature dimension under 0.18 micron even to 0.09 micron. By using a first polish step with a conventional polish pad and an oxide polish slurry, the non-uniformity of the over-fill thickness of the STI dielectric layer can be firstly removed and a much more smooth and uniform topography favorable for the HSP-CMP process the fix abrasive polishing pad can be obtained. Then the HSP-CMP process with the fix abrasive polishing pad can be performed to provide a planarized surface with accurate dimension control.

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