Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
1999-05-20
2001-05-15
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S122000
Reexamination Certificate
active
06232907
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to apparatus and methods for high speed flash analog-to-digital (A/D) conversion.
BACKGROUND AND BRIEF DESCRIPTION OF THE PRIOR ART
A conventional six-bit flash A/D converter employs an array of 63 comparators and 63 latches. Known ways to reduce this complexity are multi-step, folding and interpolation techniques.
The multi-step approach uses two or more low resolution converters in a pipeline arrangement. This results in a dramatic reduction in the number of comparators. However, one requirement of this architecture is that the decision bits from one step must be made available in a timely fashion for use by the next step. Tolerance to errors can be built into this decision using redundancy, however a complete decision must still be made. This can be a problem at high speeds because of potential metastability. In a single-step flash A/D converter, stability problems can be overcome by providing additional latches at the outputs of the comparators. However, this cannot be done in a multi-step pipeline converter.
The folding technique involves folding the input several times to map different regions of the input into a single output range. It would be ideal to use a single such folder and then subject the folded signal to a low resolution flash conversion. For instance, if a signal could be folded eight times, three bits could be realized out of this operation itself. Then, only a three-bit flash conversion would be required following the folder. Unfortunately, the folding operation introduces nonlinearity except in the vicinity of the zero crossing of the output. For this reason, practical folding A/D converters use multiple folders that are offset from each other, with the net result that there are so many folded signals that each signal must be linear only over one least significant bit (LSB). Thus, folding by itself does not result in a reduction in the number of input devices or the input capacitance, but only results in a reduction in the number of latches and simplifies the encoder.
Interpolation can be applied to any flash A/D converter, with or without folding. In the simplest form of implementation of interpolation, a six-bit converter uses only 32 input preamplifiers with their reference voltages spaced two LSBs apart. By interpolating (or averaging) between adjacent preamplifier outputs, 32 more signals can be derived that actually represent virtual preamplifier outputs for the other 32 reference levels that were skipped.
A combination of folding and interpolation has been employed in several recent implementations. However, all of these have the drawback that the folding does not reduce the number of input stages or the total input capacitance.
SUMMARY OF THE INVENTION
In accordance with the present invention, the above described problems of the prior art are minimized and there is provided a high speed A/D converter architecture which is a hybrid between a folding converter and a two-step flash A/D converter. This architecture has the advantage that it reduces by about half the number of required comparators, thereby resulting in reduction of semiconductor chip area required and a reduction in input capacitance.
The invention also provides a method of high speed A/D conversion using a combination of folding and two-step flash A/D conversion techniques.
Briefly, there is provided an A/D converter which includes a sample-and-hold circuit having an input and an output, a zero-crossing detector having an input coupled to the output of the sample-and-hold circuit and having an output indicative of a change in polarity of an input signal thereto and a polarity reverser having an input coupled to the output of the sample-and-hold circuit, a control terminal coupled to and under control of the output of the zero-crossing detector and an output terminal. A bank of comparators, preferably in a first and second array, each have inputs respectively coupled to the output of the polarity reverser, each comparator having an output. An encoder preferably having first and second portions is coupled to the output of the comparator, the first array preferably coupled to the first encoder portion and the second array preferably coupled to the second encoder portion, the encoder having an output. A multiplexer is optionally coupled to the first and second encoder portions and responsive to a predetermined signal from the second encoder portion to select signals from the outputs of one of the first and second encoders. A pair of buffers are optionally provided, a first buffer coupled between the output of the sample-and-hold circuit and both the polarity reverser and the zero crossing detector and a second buffer coupled between the output of the sample-and-hold circuit and the second array of comparators. First and second switches are optionally provided, the first switches being operational only during a first repeating time window for coupling the first buffer to the zero crossing detector and the polarity reverser and coupling the second buffer to the second array of comparators and the second switches are operational only during a second repeating time window not overlapping the first time window for coupling said second buffer to said zero crossing detector and said polarity reverser.
In accordance with a second embodiment, there is provided an A/D converter which includes a sample-and-hold circuit having an input and an output, a zero-crossing detector having an input coupled to the output of the sample-and-hold circuit and having an output indicative of a change in polarity of an input signal thereto and a reference voltage source. A polarity reverser is provided having an input coupled to the reference voltage source and the output terminal of the zero crossing detector to provide a reference voltage output of a polarity determined by the output of the zero crossing detector. A bank of comparators is provided which includes a first array of comparators and a second array of comparators, each comparator having inputs respectively coupled to the output of the polarity reverser and the reference voltage source with each comparator having an output. An encoder having a first encoder portion and a second encoder portion is provided with the first encoder portion having inputs respectively coupled to the outputs of the first array of comparators and the second encoder portion having inputs respectively coupled to the outputs of the second encoder portion. A first reference ladder is coupled to the reference voltage output and the polarity reverser, the output of said reference ladder and the output of the sample and hold circuit coupled to the input of the first array of comparators. A second reference ladder is coupled to the reference voltage source and has an output coupled to the second array of comparators along with the output of the sample and hold circuit. The circuit further includes a multiplexer coupled to the first and second encoder portions and responsive to a predetermined signal from the second encoder portion to select signals from the outputs of one of the first and second encoders. The predetermined signal is indicative of an input amplitude below a predetermined value. The circuit optionally further includes a first buffer coupled between the output of the sample-and-hold circuit and both the polarity reverser and the zero crossing detector and a second buffer coupled between the output of said sample-and-hold circuit and the second array of comparators.
REFERENCES:
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patent: 4323885 (1982-04-01), Carriere et al.
patent: 4658431 (1987-04-01), Yokota
patent: 4696018 (1987-09-01), Zaehringer et al.
patent: 5429002 (1995-07-01), Colman
patent: 5591355 (1997-01-01), Ishikawa
Nagaraj Krishnaswamy
Viswanathan T. R.
Brady III Wade James
Franz Warren L.
Paik Steven S.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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